component
AT32F403RGT6
Public Made by Adomby adom
ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AT32F403RGT6
ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)
AT32F403RGT6 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and backup registers, 2.6 V to 3.6 V; must be connected to VDD and does not support independent supply. |
| 2 | PC13 | bidirectional | GPIO (also TAMPER-RTC); it is powered through a power switch that sinks only about 3 mA, so as an output it is limited to moderate drive, 30 pF maximum load, and cannot drive LEDs. |
| 3 | PC14 | bidirectional | GPIO, also OSC32_IN for the 32.768 kHz LSE oscillator; same power-switch limit of about 3 mA and 30 pF output load as PC13. |
| 4 | PC15 | bidirectional | GPIO, also OSC32_OUT for the 32.768 kHz LSE oscillator; same power-switch limit of about 3 mA and 30 pF output load as PC13. |
| 5 | PD0 | bidirectional | Default function OSC_IN (HSE crystal input, 4-25 MHz) after reset; software can reconfigure this pin as PD0 (note 6). |
| 6 | PD1 | bidirectional | Default function OSC_OUT (HSE crystal output) after reset; software can reconfigure this pin as PD1 (note 6). |
| 7 | NRST | bidirectional | Active-low reset pin with an internal pull-up of 30-50 kΩ (40 kΩ typical); low-level input maximum 0.8 V, and pulses shorter than 66.7 µs are not filtered as reset. |
| 8 | PC0 | bidirectional | GPIO with ADC123_IN10 analog input and SDIO2_D0 alternate function. |
| 9 | PC1 | bidirectional | GPIO with ADC123_IN11 analog input and SDIO2_D1 alternate function. |
| 10 | PC2 | bidirectional | GPIO with ADC123_IN12 analog input and SDIO2_D2 alternate function. |
| 11 | PC3 | bidirectional | GPIO with ADC123_IN13 analog input and SDIO2_D3 alternate function. |
| 12 | VSSA | power_in | Analog ground for the ADC and DAC; must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC and DAC, 2.6 V to 3.6 V; must be connected to VDD, with at most 300 mV difference between VDD and VDDA during power-up and operation. |
| 14 | PA0/WKUP | bidirectional | GPIO with ADC123_IN0, TMR2_CH1, TMR5_CH1, WKUP wake-up input (rising edge exits standby), USART2_CTS and TMR2_ETR/TMR8_ETR; not 5 V tolerant. |
| 15 | PA1 | bidirectional | GPIO with ADC123_IN1, TMR2_CH2, TMR5_CH2 and USART2_RTS alternate functions; not 5 V tolerant. |
| 16 | PA2 | bidirectional | GPIO with ADC123_IN2, TMR2_CH3, TMR5_CH3, TMR9_CH1 and USART2_TX alternate functions (SDIO2_CK on remap); not 5 V tolerant. |
| 17 | PA3 | bidirectional | GPIO with ADC123_IN3, TMR2_CH4, TMR5_CH4, TMR9_CH2 and USART2_RX alternate functions (SDIO2_CMD on remap); not 5 V tolerant. |
| 18 | VSS_4 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 19 | VDD_4 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 20 | PA4 | bidirectional | GPIO with DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS and SDIO2_D4 alternate functions (SDIO2_D0 on remap); not 5 V tolerant. |
| 21 | PA5 | bidirectional | GPIO with DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK and SDIO2_D5 alternate functions (SDIO2_D1 on remap); not 5 V tolerant. |
| 22 | PA6 | bidirectional | GPIO with ADC12_IN6, TMR3_CH1, TMR13_CH1, SPI1_MISO, SDIO2_D6 and TMR8_BKIN alternate functions (SDIO2_D2 / TMR1_BKIN on remap); not 5 V tolerant. |
| 23 | PA7 | bidirectional | GPIO with ADC12_IN7, TMR3_CH2, TMR8_CH1N, TMR14_CH1, SPI1_MOSI, I2S1_SD and SDIO2_D7 alternate functions (TMR1_CH1N / SDIO2_D3 on remap); not 5 V tolerant. |
| 24 | PC4 | bidirectional | GPIO with ADC12_IN14 analog input and SDIO2_CK alternate function. |
| 25 | PC5 | bidirectional | GPIO with ADC12_IN15 analog input and SDIO2_CMD alternate function. |
| 26 | PB0 | bidirectional | GPIO with ADC12_IN8, TMR3_CH3, TMR8_CH2N and I2S1_MCK alternate functions (TMR1_CH2N on remap); not 5 V tolerant. |
| 27 | PB1 | bidirectional | GPIO with ADC12_IN9, TMR3_CH4, TMR8_CH3N and SPIM_SCK alternate functions (TMR1_CH3N on remap); not 5 V tolerant. |
| 28 | PB2 | bidirectional | 5 V tolerant GPIO whose default function is PB2/BOOT1. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO with USART3_TX, I2C2_SCL and TMR2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO with USART3_RX, I2C2_SDA and TMR2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 32 | VDD_1 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO with USART3_CK, I2C2_SMBA, SPI2_NSS, I2S2_WS and TMR1_BKIN alternate functions. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO with TMR1_CH1N, SPI2_SCK, I2S2_CK and USART3_CTS alternate functions. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO with TMR1_CH2N, TMR12_CH1, USART3_RTS and SPI2_MISO alternate functions. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO with TMR1_CH3N, TMR12_CH2, SPI2_MOSI and I2S2_SD alternate functions. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO with TMR8_CH1, I2S2_MCK and SDIO1_D6 alternate functions (TMR3_CH1 on remap). |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO with TMR8_CH2, I2S3_MCK and SDIO1_D7 alternate functions (TMR3_CH2 on remap). |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO with TMR8_CH3, SDIO1_D0 and I2S4_MCK alternate functions (TMR3_CH3 on remap). |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO with TMR8_CH4, SDIO1_D1 and I2C3_SDA alternate functions (TMR3_CH4 on remap). |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO with TMR1_CH1, CLKOUT, USART1_CK, I2C3_SCL and SPIM_NSS alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO with TMR1_CH2, USART1_TX and I2C3_SMBA alternate functions; used as USART1_TX by the bootloader. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO with TMR1_CH3 and USART1_RX alternate functions; used as USART1_RX by the bootloader. |
| 44 | PA11 | bidirectional | GPIO (not 5 V tolerant per the pin table) with USB_DM, TMR1_CH4, SPIM_IO0, USART1_CTS and CAN_RX; USB and SPIM cannot be used simultaneously, and it has an extra non-disableable 330 kΩ weak pull-down. |
| 45 | PA12 | bidirectional | GPIO (not 5 V tolerant per the pin table) with USB_DP, CAN_TX, USART1_RTS, SPIM_IO1 and TMR1_ETR; USB and SPIM cannot be used simultaneously, and it has an extra non-disableable 330 kΩ weak pull-down. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO whose default function is JTMS-SWDIO (serial-wire / JTAG debug data). |
| 47 | VSS_2 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 48 | VDD_2 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO whose default function is JTCK-SWCLK (serial-wire / JTAG debug clock). |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO whose default function is JTDI, with SPI3_NSS and I2S3_WS as listed default alternates and TMR2_CH1, SPI1_NSS, I2S1_WS and TMR2_ETR on remap. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO with UART4_TX and SDIO1_D2 alternate functions (USART3_TX on remap). |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO with UART4_RX and SDIO1_D3 alternate functions (USART3_RX on remap). |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO with UART5_TX and SDIO1_CK alternate functions (USART3_CK on remap). |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO with SDIO1_CMD, UART5_RX and TMR3_ETR alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO whose default function is JTDO (SWO/JTAG trace output), with SPI3_SCK and I2S3_CK default alternates; TRACESWO, TMR2_CH2, SPI1_SCK and I2S1_CK on remap. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO whose default function is NJTRST (JTAG reset), with SPI3_MISO default alternate; TMR3_CH1, SPI1_MISO and I2C3_SDA on remap. |
| 57 | PB5 | bidirectional | GPIO (not 5 V tolerant per the pin table) with I2C1_SMBA, SPI3_MOSI and I2S3_SD alternate functions (TMR3_CH2, SPI1_MOSI and I2S1_SD on remap). |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO with TMR4_CH1, I2C1_SCL and SPIM_IO3 alternate functions (USART1_TX on remap). |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO with TMR4_CH2, I2C1_SDA, XMC_NADV and SPIM_IO2 alternate functions (USART1_RX on remap). |
| 60 | BOOT0 | input | Boot-mode selection input; its weak pull-down resistor cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO with TMR4_CH3, TMR10_CH1 and SDIO1_D4 alternate functions (CAN_RX / I2C1_SCL on remap). |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO with TMR4_CH4, TMR11_CH1 and SDIO1_D5 alternate functions (CAN_TX / I2C1_SDA on remap). |
| 63 | VSS_3 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 64 | VDD_3 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 供电电压 (2.6至3.6伏供电和I/O引脚, 功能概述) | 2.6 | 3.6 | V | 1 | |||
| USB操作电压 | VDD | 3 | 3.6 | V | 89 | ||
| 差分输入灵敏度 | VDI | 0.2 | V | I (USB_DP，USB_DM) | 89 | ||
| 差分共模范围 | VCM | 0.8 | 2.5 | V | 包含VDI范围 | 89 | |
| 单端接收器阀值 | VSE | 1.3 | 2 | V | 89 | ||
| 静态输出低电平 | VOL | 0.3 | V | 1.5 kΩ的RL接至3.6 V | 89 | ||
| 静态输出高电平 | VOH | 2.8 | 3.6 | V | 15 kΩ的RL接至VSS | 89 | |
| USB_DP内部上拉电阻 | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 89 |
| USB收发器启动时间 | tSTARTUP | 1 | μs | 89 | |||
| 上升下降时间匹配 tr/tf | trfm | 90 | 110 | % | 89 | ||
| 上升时间 (USB全速) | tr | 4 | 20 | ns | CL ≤ 50 pF | 89 | |
| 下降时间 (USB全速) | tf | 4 | 20 | ns | CL ≤ 50 pF | 89 | |
| 输出信号交叉电压 | VCRS | 1.3 | 2 | V | 89 | ||
| 数据传输模式下的时钟频率 | fPP | 0 | 48 | MHz | CL ≤ 30 pF | 88 | |
| 时钟低时间 | tW(CKL) | 32 | ns | CL ≤ 30 pF | 88 | ||
| 时钟高时间 | tW(CKH) | 30 | ns | CL ≤ 30 pF | 88 | ||
| 时钟上升时间 (SDIO) | tr | 4 | ns | CL ≤ 30 pF | 88 | ||
| 时钟下降时间 (SDIO) | tf | 5 | ns | CL ≤ 30 pF | 88 | ||
| 时钟建立时间 | tISU | 2 | ns | CL ≤ 30 pF | 88 | ||
| 时钟保持时间 | tIH | 0 | ns | CL ≤ 30 pF | 88 | ||
| 输出有效时间 | tOV | 6 | ns | MMC和SD高速模式; CL ≤ 30 pF | 88 | ||
| 输出保持时间 | tOH | 0 | ns | MMC和SD高速模式; CL ≤ 30 pF | 88 | ||
| 输出有效默认时间 | tOVD | 7 | ns | SD默认模式; CL ≤ 30 pF | 88 | ||
| 输出保持默认时间 | tOHD | 0.5 | ns | SD默认模式; CL ≤ 30 pF | 88 | ||
| 供电电压 (ADC) | VDDA | 2.6 | 3.6 | V | 90 | ||
| 正参考电压 | VREF+ | 2.6 | V | 90 | |||
| 在VDDA输入脚上的电流 | IDDA | 600 | μA | 90 | |||
| 在VREF输入脚上的电流 | IVREF | 350 | μA | 90 | |||
| ADC时钟频率 | fADC | 0.6 | 28 | MHz | 90 | ||
| 采样速率 | fS | 0.05 | 2 | MHz | 90 | ||
| 外部触发频率 | fTRIG | 1.65 | MHz | fADC = 28 MHz | 90 | ||
| 外部触发频率 | fTRIG | 17 | 1/fADC | 90 | |||
| 转换电压范围 | VAIN | 0 | V | 90 | |||
| 注入触发转换时延 | tlat | 107 | ns | fADC = 28 MHz | 90 | ||
| 注入触发转换时延 | tlat | 3 | 1/fADC | 90 | |||
| 常规触发转换时延 | tlatr | 71.4 | μs | fADC = 28 MHz | 90 | ||
| 常规触发转换时延 | tlatr | 2 | 1/fADC | 90 | |||
| 采样时间 | tS | 0.053 | 8.55 | μs | fADC = 28 MHz | 90 | |
| 采样时间 | tS | 1.5 | 239.5 | 1/fADC | 90 | ||
| 总转换时间(包括采样时间) | tCONV | 0.5 | 9 | μs | fADC = 28 MHz | 90 | |
| 总转换时间(包括采样时间) | tCONV | 14 | 252 | 1/fADC | 采样tS + 逐步逼近12.5 | 90 | |
| 内部8 MHz RC振荡器精度 (25 °C) | -1 | 1 | % | 25 °C | 1 | ||
| 内部8 MHz RC振荡器精度 (全温度) | -2.5 | 2.5 | % | 全温度 | 1 |
CAD (KiCad official)
- Symbol:
AT32F403RGT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
at32f403rgt6-etched.step/at32f403rgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f403rgt6.step/at32f403rgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (109 pp, sha256
f81ddc4b12983013, retrieved 2026-11-05, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AT32F403RGT6
**ARTERY** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)
AT32F403RGT6 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and backup registers, 2.6 V to 3.6 V; must be connected to VDD and does not support independent supply. |
| 2 | PC13 | bidirectional | GPIO (also TAMPER-RTC); it is powered through a power switch that sinks only about 3 mA, so as an output it is limited to moderate drive, 30 pF maximum load, and cannot drive LEDs. |
| 3 | PC14 | bidirectional | GPIO, also OSC32_IN for the 32.768 kHz LSE oscillator; same power-switch limit of about 3 mA and 30 pF output load as PC13. |
| 4 | PC15 | bidirectional | GPIO, also OSC32_OUT for the 32.768 kHz LSE oscillator; same power-switch limit of about 3 mA and 30 pF output load as PC13. |
| 5 | PD0 | bidirectional | Default function OSC_IN (HSE crystal input, 4-25 MHz) after reset; software can reconfigure this pin as PD0 (note 6). |
| 6 | PD1 | bidirectional | Default function OSC_OUT (HSE crystal output) after reset; software can reconfigure this pin as PD1 (note 6). |
| 7 | NRST | bidirectional | Active-low reset pin with an internal pull-up of 30-50 kΩ (40 kΩ typical); low-level input maximum 0.8 V, and pulses shorter than 66.7 µs are not filtered as reset. |
| 8 | PC0 | bidirectional | GPIO with ADC123_IN10 analog input and SDIO2_D0 alternate function. |
| 9 | PC1 | bidirectional | GPIO with ADC123_IN11 analog input and SDIO2_D1 alternate function. |
| 10 | PC2 | bidirectional | GPIO with ADC123_IN12 analog input and SDIO2_D2 alternate function. |
| 11 | PC3 | bidirectional | GPIO with ADC123_IN13 analog input and SDIO2_D3 alternate function. |
| 12 | VSSA | power_in | Analog ground for the ADC and DAC; must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC and DAC, 2.6 V to 3.6 V; must be connected to VDD, with at most 300 mV difference between VDD and VDDA during power-up and operation. |
| 14 | PA0/WKUP | bidirectional | GPIO with ADC123_IN0, TMR2_CH1, TMR5_CH1, WKUP wake-up input (rising edge exits standby), USART2_CTS and TMR2_ETR/TMR8_ETR; not 5 V tolerant. |
| 15 | PA1 | bidirectional | GPIO with ADC123_IN1, TMR2_CH2, TMR5_CH2 and USART2_RTS alternate functions; not 5 V tolerant. |
| 16 | PA2 | bidirectional | GPIO with ADC123_IN2, TMR2_CH3, TMR5_CH3, TMR9_CH1 and USART2_TX alternate functions (SDIO2_CK on remap); not 5 V tolerant. |
| 17 | PA3 | bidirectional | GPIO with ADC123_IN3, TMR2_CH4, TMR5_CH4, TMR9_CH2 and USART2_RX alternate functions (SDIO2_CMD on remap); not 5 V tolerant. |
| 18 | VSS_4 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 19 | VDD_4 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 20 | PA4 | bidirectional | GPIO with DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS and SDIO2_D4 alternate functions (SDIO2_D0 on remap); not 5 V tolerant. |
| 21 | PA5 | bidirectional | GPIO with DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK and SDIO2_D5 alternate functions (SDIO2_D1 on remap); not 5 V tolerant. |
| 22 | PA6 | bidirectional | GPIO with ADC12_IN6, TMR3_CH1, TMR13_CH1, SPI1_MISO, SDIO2_D6 and TMR8_BKIN alternate functions (SDIO2_D2 / TMR1_BKIN on remap); not 5 V tolerant. |
| 23 | PA7 | bidirectional | GPIO with ADC12_IN7, TMR3_CH2, TMR8_CH1N, TMR14_CH1, SPI1_MOSI, I2S1_SD and SDIO2_D7 alternate functions (TMR1_CH1N / SDIO2_D3 on remap); not 5 V tolerant. |
| 24 | PC4 | bidirectional | GPIO with ADC12_IN14 analog input and SDIO2_CK alternate function. |
| 25 | PC5 | bidirectional | GPIO with ADC12_IN15 analog input and SDIO2_CMD alternate function. |
| 26 | PB0 | bidirectional | GPIO with ADC12_IN8, TMR3_CH3, TMR8_CH2N and I2S1_MCK alternate functions (TMR1_CH2N on remap); not 5 V tolerant. |
| 27 | PB1 | bidirectional | GPIO with ADC12_IN9, TMR3_CH4, TMR8_CH3N and SPIM_SCK alternate functions (TMR1_CH3N on remap); not 5 V tolerant. |
| 28 | PB2 | bidirectional | 5 V tolerant GPIO whose default function is PB2/BOOT1. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO with USART3_TX, I2C2_SCL and TMR2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO with USART3_RX, I2C2_SDA and TMR2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 32 | VDD_1 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO with USART3_CK, I2C2_SMBA, SPI2_NSS, I2S2_WS and TMR1_BKIN alternate functions. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO with TMR1_CH1N, SPI2_SCK, I2S2_CK and USART3_CTS alternate functions. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO with TMR1_CH2N, TMR12_CH1, USART3_RTS and SPI2_MISO alternate functions. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO with TMR1_CH3N, TMR12_CH2, SPI2_MOSI and I2S2_SD alternate functions. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO with TMR8_CH1, I2S2_MCK and SDIO1_D6 alternate functions (TMR3_CH1 on remap). |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO with TMR8_CH2, I2S3_MCK and SDIO1_D7 alternate functions (TMR3_CH2 on remap). |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO with TMR8_CH3, SDIO1_D0 and I2S4_MCK alternate functions (TMR3_CH3 on remap). |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO with TMR8_CH4, SDIO1_D1 and I2C3_SDA alternate functions (TMR3_CH4 on remap). |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO with TMR1_CH1, CLKOUT, USART1_CK, I2C3_SCL and SPIM_NSS alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO with TMR1_CH2, USART1_TX and I2C3_SMBA alternate functions; used as USART1_TX by the bootloader. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO with TMR1_CH3 and USART1_RX alternate functions; used as USART1_RX by the bootloader. |
| 44 | PA11 | bidirectional | GPIO (not 5 V tolerant per the pin table) with USB_DM, TMR1_CH4, SPIM_IO0, USART1_CTS and CAN_RX; USB and SPIM cannot be used simultaneously, and it has an extra non-disableable 330 kΩ weak pull-down. |
| 45 | PA12 | bidirectional | GPIO (not 5 V tolerant per the pin table) with USB_DP, CAN_TX, USART1_RTS, SPIM_IO1 and TMR1_ETR; USB and SPIM cannot be used simultaneously, and it has an extra non-disableable 330 kΩ weak pull-down. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO whose default function is JTMS-SWDIO (serial-wire / JTAG debug data). |
| 47 | VSS_2 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 48 | VDD_2 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO whose default function is JTCK-SWCLK (serial-wire / JTAG debug clock). |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO whose default function is JTDI, with SPI3_NSS and I2S3_WS as listed default alternates and TMR2_CH1, SPI1_NSS, I2S1_WS and TMR2_ETR on remap. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO with UART4_TX and SDIO1_D2 alternate functions (USART3_TX on remap). |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO with UART4_RX and SDIO1_D3 alternate functions (USART3_RX on remap). |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO with UART5_TX and SDIO1_CK alternate functions (USART3_CK on remap). |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO with SDIO1_CMD, UART5_RX and TMR3_ETR alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO whose default function is JTDO (SWO/JTAG trace output), with SPI3_SCK and I2S3_CK default alternates; TRACESWO, TMR2_CH2, SPI1_SCK and I2S1_CK on remap. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO whose default function is NJTRST (JTAG reset), with SPI3_MISO default alternate; TMR3_CH1, SPI1_MISO and I2C3_SDA on remap. |
| 57 | PB5 | bidirectional | GPIO (not 5 V tolerant per the pin table) with I2C1_SMBA, SPI3_MOSI and I2S3_SD alternate functions (TMR3_CH2, SPI1_MOSI and I2S1_SD on remap). |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO with TMR4_CH1, I2C1_SCL and SPIM_IO3 alternate functions (USART1_TX on remap). |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO with TMR4_CH2, I2C1_SDA, XMC_NADV and SPIM_IO2 alternate functions (USART1_RX on remap). |
| 60 | BOOT0 | input | Boot-mode selection input; its weak pull-down resistor cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO with TMR4_CH3, TMR10_CH1 and SDIO1_D4 alternate functions (CAN_RX / I2C1_SCL on remap). |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO with TMR4_CH4, TMR11_CH1 and SDIO1_D5 alternate functions (CAN_TX / I2C1_SDA on remap). |
| 63 | VSS_3 | power_in | Ground pin for the digital supply domain; must be connected to VSS. |
| 64 | VDD_3 | power_in | Digital supply pin for I/O and the internal regulator, 2.6 V to 3.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 供电电压 (2.6至3.6伏供电和I/O引脚, 功能概述) | | 2.6 | | 3.6 | V | | 1 |
| USB操作电压 | VDD | 3 | | 3.6 | V | | 89 |
| 差分输入灵敏度 | VDI | 0.2 | | | V | I (USB_DP，USB_DM) | 89 |
| 差分共模范围 | VCM | 0.8 | | 2.5 | V | 包含VDI范围 | 89 |
| 单端接收器阀值 | VSE | 1.3 | | 2 | V | | 89 |
| 静态输出低电平 | VOL | | | 0.3 | V | 1.5 kΩ的RL接至3.6 V | 89 |
| 静态输出高电平 | VOH | 2.8 | | 3.6 | V | 15 kΩ的RL接至VSS | 89 |
| USB_DP内部上拉电阻 | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 89 |
| USB收发器启动时间 | tSTARTUP | | | 1 | μs | | 89 |
| 上升下降时间匹配 tr/tf | trfm | 90 | | 110 | % | | 89 |
| 上升时间 (USB全速) | tr | 4 | | 20 | ns | CL ≤ 50 pF | 89 |
| 下降时间 (USB全速) | tf | 4 | | 20 | ns | CL ≤ 50 pF | 89 |
| 输出信号交叉电压 | VCRS | 1.3 | | 2 | V | | 89 |
| 数据传输模式下的时钟频率 | fPP | 0 | | 48 | MHz | CL ≤ 30 pF | 88 |
| 时钟低时间 | tW(CKL) | 32 | | | ns | CL ≤ 30 pF | 88 |
| 时钟高时间 | tW(CKH) | 30 | | | ns | CL ≤ 30 pF | 88 |
| 时钟上升时间 (SDIO) | tr | | | 4 | ns | CL ≤ 30 pF | 88 |
| 时钟下降时间 (SDIO) | tf | | | 5 | ns | CL ≤ 30 pF | 88 |
| 时钟建立时间 | tISU | 2 | | | ns | CL ≤ 30 pF | 88 |
| 时钟保持时间 | tIH | 0 | | | ns | CL ≤ 30 pF | 88 |
| 输出有效时间 | tOV | | | 6 | ns | MMC和SD高速模式; CL ≤ 30 pF | 88 |
| 输出保持时间 | tOH | 0 | | | ns | MMC和SD高速模式; CL ≤ 30 pF | 88 |
| 输出有效默认时间 | tOVD | | | 7 | ns | SD默认模式; CL ≤ 30 pF | 88 |
| 输出保持默认时间 | tOHD | 0.5 | | | ns | SD默认模式; CL ≤ 30 pF | 88 |
| 供电电压 (ADC) | VDDA | 2.6 | | 3.6 | V | | 90 |
| 正参考电压 | VREF+ | 2.6 | | | V | | 90 |
| 在VDDA输入脚上的电流 | IDDA | | | 600 | μA | | 90 |
| 在VREF输入脚上的电流 | IVREF | | | 350 | μA | | 90 |
| ADC时钟频率 | fADC | 0.6 | | 28 | MHz | | 90 |
| 采样速率 | fS | 0.05 | | 2 | MHz | | 90 |
| 外部触发频率 | fTRIG | | | 1.65 | MHz | fADC = 28 MHz | 90 |
| 外部触发频率 | fTRIG | | | 17 | 1/fADC | | 90 |
| 转换电压范围 | VAIN | 0 | | | V | | 90 |
| 注入触发转换时延 | tlat | | | 107 | ns | fADC = 28 MHz | 90 |
| 注入触发转换时延 | tlat | | | 3 | 1/fADC | | 90 |
| 常规触发转换时延 | tlatr | | | 71.4 | μs | fADC = 28 MHz | 90 |
| 常规触发转换时延 | tlatr | | | 2 | 1/fADC | | 90 |
| 采样时间 | tS | 0.053 | | 8.55 | μs | fADC = 28 MHz | 90 |
| 采样时间 | tS | 1.5 | | 239.5 | 1/fADC | | 90 |
| 总转换时间(包括采样时间) | tCONV | 0.5 | | 9 | μs | fADC = 28 MHz | 90 |
| 总转换时间(包括采样时间) | tCONV | 14 | | 252 | 1/fADC | 采样tS + 逐步逼近12.5 | 90 |
| 内部8 MHz RC振荡器精度 (25 °C) | | -1 | | 1 | % | 25 °C | 1 |
| 内部8 MHz RC振荡器精度 (全温度) | | -2.5 | | 2.5 | % | 全温度 | 1 |
## CAD (KiCad official)
- Symbol: `AT32F403RGT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `at32f403rgt6-etched.step` / `at32f403rgt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f403rgt6.step` / `at32f403rgt6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ARTERY datasheet](docs/at32f403rgt6-datasheet.pdf) (109 pp, sha256 `f81ddc4b12983013`, retrieved 2026-11-05, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/at32f403rgt6-datasheet.pdf)