# AT32F403AVGT7

**ARTERY** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

AT32F403AVGT7 from ARTERY, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5V-tolerant (FT) I/O; alternate functions SPI4_SCK/I2S4_CK, XMC_A23, TRACECK. |
| 2 | PE3 | bidirectional | 5V-tolerant (FT) I/O; alternate functions XMC_A19, TRACED0. |
| 3 | PE4 | bidirectional | 5V-tolerant (FT) I/O; alternate functions SPI4_NSS/I2S4_WS, XMC_A20, TRACED1. |
| 4 | PE5 | bidirectional | 5V-tolerant (FT) I/O; alternate functions SPI4_MISO, XMC_A21, TRACED2; remap TMR9_CH1. |
| 5 | PE6 | bidirectional | 5V-tolerant (FT) I/O; alternate functions SPI4_MOSI/I2S4_SD, XMC_A22, TRACED3; remap TMR9_CH2. |
| 6 | VBAT | power_in | Backup supply, 1.8 to 3.6 V, powering RTC, 32 kHz oscillator and backup registers when VDD is off. |
| 7 | PC13/TAMPER-RTC | bidirectional | TC I/O powered via the backup power switch (3 mA sink limit, 30 pF max load, not usable as a current source); function TAMPER-RTC. |
| 8 | PC14/OSC32_IN | bidirectional | TC I/O powered via the backup power switch (3 mA limit); 32 kHz crystal oscillator input OSC32_IN. |
| 9 | PC15/OSC32_OUT | bidirectional | TC I/O powered via the backup power switch (3 mA limit); 32 kHz crystal oscillator output OSC32_OUT. |
| 10 | VSS_5 | power_in | Ground pin 5. |
| 11 | VDD_5 | power_in | Digital supply pin 5, 2.6 to 3.6 V. |
| 12 | OSC_IN | input | Input of the 4 to 25 MHz HSE crystal oscillator or external clock input. |
| 13 | OSC_OUT | output | Output of the 4 to 25 MHz HSE crystal oscillator. |
| 14 | NRST | bidirectional | Device reset input/output, active low, with internal pull-up. |
| 15 | PC0 | bidirectional | 5V-tolerant analog-capable (FTa) I/O; ADC123_IN10, SDIO2_D0. |
| 16 | PC1 | bidirectional | FTa I/O; ADC123_IN11, SDIO2_D1. |
| 17 | PC2 | bidirectional | FTa I/O; ADC123_IN12, SDIO2_D2; remap UART8_TX, XMC_NWE. |
| 18 | PC3 | bidirectional | FTa I/O; ADC123_IN13, SDIO2_D3, XMC_A0; remap UART8_RX. |
| 19 | VSSA | power_in | Analog ground; must be connected to VSS. |
| 20 | VREF- | power_in | Negative ADC/DAC reference voltage input (present on 100-pin package only). |
| 21 | VREF+ | power_in | Positive ADC/DAC reference voltage, 2.6 V to VDDA (present on 100-pin package only). |
| 22 | VDDA | power_in | Analog supply for ADC and DAC, 2.6 to 3.6 V; must be connected to VDD. |
| 23 | PA0/WKUP | bidirectional | TC I/O; ADC123_IN0, WKUP, USART2_CTS, TMR2_CH1/ETR, TMR5_CH1, TMR8_ETR; remap UART4_TX. |
| 24 | PA1 | bidirectional | FTa I/O; ADC123_IN1, USART2_RTS, TMR2_CH2, TMR5_CH2; remap UART4_RX. |
| 25 | PA2 | bidirectional | FTa I/O; ADC123_IN2, USART2_TX, TMR2_CH3, TMR5_CH3, TMR9_CH1; remap SDIO2_CK, XMC_D4. |
| 26 | PA3 | bidirectional | FTa I/O; ADC123_IN3, USART2_RX, TMR2_CH4, TMR5_CH4, TMR9_CH2; remap I2S2_MCK, SDIO2_CMD, XMC_D5. |
| 27 | VSS_4 | power_in | Ground pin 4. |
| 28 | VDD_4 | power_in | Digital supply pin 4, 2.6 to 3.6 V. |
| 29 | PA4 | bidirectional | FTa I/O; DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS/I2S1_WS, SDIO2_D4; remap USART6_TX, SPI3_NSS, XMC_D6. |
| 30 | PA5 | bidirectional | FTa I/O; DAC_OUT2, ADC12_IN5, SPI1_SCK/I2S1_CK, SDIO2_D5; remap USART6_RX, SDIO2_D1, XMC_D7. |
| 31 | PA6 | bidirectional | FTa I/O; ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN, TMR13_CH1; remap I2S2_MCK, TMR1_BKIN. |
| 32 | PA7 | bidirectional | FTa I/O; ADC12_IN7, SPI1_MOSI/I2S1_SD, SDIO2_D7, TMR3_CH2, TMR8_CH1N, TMR14_CH1; remap TMR1_CH1N. |
| 33 | PC4 | bidirectional | FTa I/O; ADC12_IN14, SDIO2_CK, XMC_NE4. |
| 34 | PC5 | bidirectional | FTa I/O; ADC12_IN15, SDIO2_CMD; remap XMC_NOE. |
| 35 | PB0 | bidirectional | FTa I/O; ADC12_IN8, I2S1_MCK, TMR3_CH3, TMR8_CH2N; remap TMR1_CH2N. |
| 36 | PB1 | bidirectional | FTa I/O; ADC12_IN9, SPIM_SCK, TMR3_CH4, TMR8_CH3N; remap TMR1_CH3N. |
| 37 | PB2/BOOT1 | bidirectional | 5V-tolerant (FT) I/O that also serves as BOOT1 boot-mode select. |
| 38 | PE7 | bidirectional | FT I/O; UART7_RX, XMC_D4; remap TMR1_ETR. |
| 39 | PE8 | bidirectional | FT I/O; UART7_TX, XMC_D5; remap TMR1_CH1N. |
| 40 | PE9 | bidirectional | FT I/O; XMC_D6; remap TMR1_CH1. |
| 41 | PE10 | bidirectional | FT I/O; XMC_D7; remap TMR1_CH2N. |
| 42 | PE11 | bidirectional | FT I/O; XMC_D8; remap SPI4_SCK/I2S4_CK, TMR1_CH2. |
| 43 | PE12 | bidirectional | FT I/O; XMC_D9; remap SPI4_NSS/I2S4_WS, TMR1_CH3N. |
| 44 | PE13 | bidirectional | FT I/O; XMC_D10; remap SPI4_MISO, TMR1_CH3. |
| 45 | PE14 | bidirectional | FT I/O; XMC_D11; remap SPI4_MOSI/I2S4_SD, TMR1_CH4. |
| 46 | PE15 | bidirectional | FT I/O; XMC_D12; remap TMR1_BKIN. |
| 47 | PB10 | bidirectional | FT I/O; USART3_TX, I2C2_SCL; remap I2S3_MCK, SPIM_IO0, TMR2_CH3. |
| 48 | PB11 | bidirectional | FT I/O; USART3_RX, I2C2_SDA; remap SPIM_IO1, TMR2_CH4. |
| 49 | VSS_1 | power_in | Ground pin 1. |
| 50 | VDD_1 | power_in | Digital supply pin 1, 2.6 to 3.6 V. |
| 51 | PB12 | bidirectional | FT I/O; USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS/I2S2_WS, TMR1_BKIN; remap XMC_D13. |
| 52 | PB13 | bidirectional | FT I/O; USART3_CTS, CAN2_TX, SPI2_SCK/I2S2_CK, TMR1_CH1N. |
| 53 | PB14 | bidirectional | FT I/O; USART3_RTS, SPI2_MISO, I2S2ext_SD, TMR1_CH2N, TMR12_CH1; remap XMC_D0. |
| 54 | PB15 | bidirectional | FT I/O; SPI2_MOSI/I2S2_SD, TMR1_CH3N, TMR12_CH2. |
| 55 | PD8 | bidirectional | FT I/O; XMC_D13; remap USART3_TX. |
| 56 | PD9 | bidirectional | FT I/O; XMC_D14; remap USART3_RX. |
| 57 | PD10 | bidirectional | FT I/O; XMC_D15; remap USART3_CK. |
| 58 | PD11 | bidirectional | FT I/O; XMC_A16; remap USART3_CTS. |
| 59 | PD12 | bidirectional | FT I/O; XMC_A17; remap USART3_RTS, TMR4_CH1. |
| 60 | PD13 | bidirectional | FT I/O; XMC_A18; remap TMR4_CH2. |
| 61 | PD14 | bidirectional | FT I/O; XMC_D0; remap TMR4_CH3. |
| 62 | PD15 | bidirectional | FT I/O; XMC_D1; remap TMR4_CH4. |
| 63 | PC6 | bidirectional | FT I/O; USART6_TX, I2S2_MCK, SDIO1_D6, TMR8_CH1; remap XMC_D1, TMR3_CH1. |
| 64 | PC7 | bidirectional | FT I/O; USART6_RX, I2S3_MCK, SDIO1_D7, TMR8_CH2; remap TMR3_CH2. |
| 65 | PC8 | bidirectional | FT I/O; USART6_CK, I2S4_MCK, SDIO1_D0, TMR8_CH3; remap TMR3_CH3. |
| 66 | PC9 | bidirectional | FT I/O; I2C3_SDA, SDIO1_D1, TMR8_CH4; remap TMR3_CH4. |
| 67 | PA8 | bidirectional | FT I/O; CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS, TMR1_CH1. |
| 68 | PA9 | bidirectional | FT I/O; USART1_TX, I2C3_SMBA, TMR1_CH2. |
| 69 | PA10 | bidirectional | FT I/O; USART1_RX, TMR1_CH3; remap I2S4_MCK. |
| 70 | PA11 | bidirectional | TC I/O; USB_DM, USART1_CTS, CAN1_RX, SPIM_IO0, TMR1_CH4. |
| 71 | PA12 | bidirectional | TC I/O; USB_DP, USART1_RTS, CAN1_TX, SPIM_IO1, TMR1_ETR. |
| 72 | PA13/JTMS-SWDIO | bidirectional | FT I/O; default function JTMS/SWDIO debug pin; PA13 after remap. |
| 73 | NC | unconnected | Not connected on the LQFP100 package. |
| 74 | VSS_2 | power_in | Ground pin 2. |
| 75 | VDD_2 | power_in | Digital supply pin 2, 2.6 to 3.6 V. |
| 76 | PA14/JTCK-SWCLK | bidirectional | FT I/O; default function JTCK/SWCLK debug pin; PA14 after remap. |
| 77 | PA15/JTDI | bidirectional | FT I/O; default JTDI, SPI3_NSS/I2S3_WS; remap PA15, SPI1_NSS/I2S1_WS, TMR2_CH1/ETR. |
| 78 | PC10 | bidirectional | FT I/O; UART4_TX, SDIO1_D2; remap USART3_TX, SPI3_SCK/I2S3_CK. |
| 79 | PC11 | bidirectional | FT I/O; UART4_RX, SDIO1_D3; remap USART3_RX, SPI3_MISO, I2S3ext_SD, XMC_D2. |
| 80 | PC12 | bidirectional | FT I/O; UART5_TX, SDIO1_CK; remap USART3_CK, SPI3_MOSI/I2S3_SD, XMC_D3. |
| 81 | PD0 | bidirectional | FT I/O; XMC_D2; remap CAN1_RX. |
| 82 | PD1 | bidirectional | FT I/O; XMC_D3; remap CAN1_TX. |
| 83 | PD2 | bidirectional | FT I/O; UART5_RX, SDIO1_CMD, TMR3_ETR; remap XMC_NWE. |
| 84 | PD3 | bidirectional | FT I/O; XMC_CLK; remap USART2_CTS. |
| 85 | PD4 | bidirectional | FT I/O; XMC_NOE; remap USART2_RTS. |
| 86 | PD5 | bidirectional | FT I/O; XMC_NWE; remap USART2_TX (also bootloader USART2_TX on this part). |
| 87 | PD6 | bidirectional | FT I/O; XMC_NWAIT; remap USART2_RX (also bootloader USART2_RX on this part). |
| 88 | PD7 | bidirectional | FT I/O; XMC_NE1/XMC_NCE2; remap USART2_CK. |
| 89 | PB3/JTDO | bidirectional | FT I/O; default JTDO, SPI3_SCK/I2S3_CK; remap PB3, UART7_RX, SPI1_SCK/I2S1_CK, TRACESWO, TMR2_CH2. |
| 90 | PB4/NJTRST | bidirectional | FT I/O; default NJTRST, SPI3_MISO, I2S3ext_SD; remap PB4, SPI1_MISO, I2C3_SDA, UART7_TX, TMR3_CH1. |
| 91 | PB5 | bidirectional | FT I/O; SPI3_MOSI/I2S3_SD, I2C1_SMBA; remap SPI1_MOSI/I2S1_SD, CAN2_RX, TMR3_CH2. |
| 92 | PB6 | bidirectional | FT I/O; I2C1_SCL, SPIM_IO3, TMR4_CH1; remap USART1_TX, I2S1_MCK, SPI4_NSS/I2S4_WS, CAN2_TX. |
| 93 | PB7 | bidirectional | FT I/O; I2C1_SDA, XMC_NADV, SPIM_IO2 (SPIM unusable when XMC is used), TMR4_CH2; remap USART1_RX, SPI4_SCK/I2S4_CK. |
| 94 | BOOT0 | input | Boot mode selection input (internal weak pull-down that cannot be disabled). |
| 95 | PB8 | bidirectional | FT I/O; SDIO1_D4, TMR4_CH3, TMR10_CH1; remap UART5_RX, SPI4_MISO, I2C1_SCL, CAN1_RX. |
| 96 | PB9 | bidirectional | FT I/O; SDIO1_D5, TMR4_CH4, TMR11_CH1; remap UART5_TX, SPI4_MOSI/I2S4_SD, I2C1_SDA, CAN1_TX. |
| 97 | PE0 | bidirectional | FT I/O; UART8_RX, XMC_NBL0, TMR4_ETR. |
| 98 | PE1 | bidirectional | FT I/O; UART8_TX, XMC_NBL1. |
| 99 | VSS_3 | power_in | Ground pin 3. |
| 100 | VDD_3 | power_in | Digital supply pin 3, 2.6 to 3.6 V; the 4.7 µF capacitor must connect here. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## CAD (KiCad official)

- Symbol: `AT32F403AVGT7`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `at32f403avgt7-etched.step` / `at32f403avgt7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f403avgt7.step` / `at32f403avgt7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ARTERY datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906219007823872) (96 pp, sha256 `602689c1ae94c051`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at32f403avgt7-datasheet.pdf)