AT32F403AVCT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

AT32F403AVCT7 from ARTERY, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI4_SCK/I2S4_CK, XMC_A23 and TRACECK.
2	PE3	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_A19 and TRACED0.
3	PE4	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI4_NSS/I2S4_WS, XMC_A20 and TRACED1.
4	PE5	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI4_MISO, XMC_A21, TRACED2 and TMR9_CH1.
5	PE6	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI4_MOSI/I2S4_SD, XMC_A22, TRACED3 and TMR9_CH2.
6	VBAT	power_in	Backup supply, 1.8 V to 3.6 V, powering the RTC, the 32 kHz oscillator and the backup registers when VDD is off.
7	PC13/TAMPER-RTC	bidirectional	Standard-level (TC) I/O with TAMPER-RTC function; supplied through a power switch limited to 3 mA, so as an output it is limited to medium drive, 30 pF maximum load, and must not source current (e.g. LEDs).
8	PC14/OSC32_IN	bidirectional	Standard-level (TC) I/O with OSC32_IN function; same 3 mA power-switch limit as PC13 applies when used as output.
9	PC15/OSC32_OUT	bidirectional	Standard-level (TC) I/O with OSC32_OUT function; same 3 mA power-switch limit as PC13 applies when used as output.
10	VSS_5	power_in	Ground pin; must be connected to the external ground system.
11	VDD_5	power_in	Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator.
12	OSC_IN	input	HSE oscillator input for a 4 to 25 MHz crystal/resonator or external user clock.
13	OSC_OUT	output	HSE oscillator output for the 4 to 25 MHz crystal/resonator.
14	NRST	bidirectional	Active-low reset pin with an internal pull-up (RPU 30 to 50 kΩ) that cannot be disconnected.
15	PC0	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN10 and SDIO2_D0.
16	PC1	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN11 and SDIO2_D1.
17	PC2	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN12, SDIO2_D2, UART8_TX and XMC_NWE.
18	PC3	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN13, SDIO2_D3, XMC_A0 and UART8_RX.
19	VSSA	power_in	Analog ground for the ADC and DAC; must be connected to VSS.
20	VREF-	power_in	Negative reference voltage input for the ADC and DAC; VREF- is included in the 50 mV maximum ground-difference limit.
21	VREF+	power_in	Positive reference voltage input for the ADC and DAC, from 2.6 V up to VDDA (may be tied to VDDA).
22	VDDA	power_in	Analog supply, 2.6 V to 3.6 V, for the ADC and DAC; must be connected to VDD (up to 300 mV difference allowed).
23	PA0-WKUP	bidirectional	Standard-level (TC) I/O; wake-up input WKUP; alternate functions ADC123_IN0, USART2_CTS, TMR2_CH1, TMR2_ETR, TMR5_CH1, TMR8_ETR and UART4_TX.
24	PA1	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN1, USART2_RTS, TMR2_CH2, TMR5_CH2 and UART4_RX.
25	PA2	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN2, USART2_TX, TMR2_CH3, TMR5_CH3, TMR9_CH1, SDIO2_CK and XMC_D4.
26	PA3	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN3, USART2_RX, TMR2_CH4, TMR5_CH4, TMR9_CH2, I2S2_MCK, SDIO2_CMD and XMC_D5.
27	VSS_4	power_in	Ground pin; must be connected to the external ground system.
28	VDD_4	power_in	Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator.
29	PA4	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS, SDIO2_D4, USART6_TX, SPI3_NSS, I2S3_WS, SDIO2_D0 and XMC_D6.
30	PA5	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK, SDIO2_D5, USART6_RX, SDIO2_D1 and XMC_D7.
31	PA6	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN, TMR13_CH1, I2S2_MCK, SDIO2_D2 and TMR1_BKIN.
32	PA7	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN7, SPI1_MOSI, I2S1_SD, SDIO2_D7, TMR3_CH2, TMR8_CH1N, TMR14_CH1, SDIO2_D3 and TMR1_CH1N.
33	PC4	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN14, SDIO2_CK and XMC_NE4.
34	PC5	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN15, SDIO2_CMD and XMC_NOE.
35	PB0	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN8, I2S1_MCK, TMR3_CH3, TMR8_CH2N and TMR1_CH2N.
36	PB1	bidirectional	5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN9, SPIM_SCK, TMR3_CH4, TMR8_CH3N and TMR1_CH3N.
37	PB2/BOOT1	bidirectional	5 V-tolerant (FT) GPIO that also serves as the BOOT1 boot-mode configuration input.
38	PE7	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART7_RX, XMC_D4 and TMR1_ETR.
39	PE8	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART7_TX, XMC_D5 and TMR1_CH1N.
40	PE9	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D6 and TMR1_CH1.
41	PE10	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D7 and TMR1_CH2N.
42	PE11	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D8, SPI4_SCK, I2S4_CK and TMR1_CH2.
43	PE12	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D9, SPI4_NSS, I2S4_WS and TMR1_CH3N.
44	PE13	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D10, SPI4_MISO and TMR1_CH3.
45	PE14	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D11, SPI4_MOSI, I2S4_SD and TMR1_CH4.
46	PE15	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D12 and TMR1_BKIN.
47	PB10	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART3_TX, I2C2_SCL, I2S3_MCK, SPIM_IO0 and TMR2_CH3.
48	PB11	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART3_RX, I2C2_SDA, SPIM_IO1 and TMR2_CH4.
49	VSS_1	power_in	Ground pin; must be connected to the external ground system.
50	VDD_1	power_in	Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator.
51	PB12	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS, I2S2_WS, TMR1_BKIN and XMC_D13.
52	PB13	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART3_CTS, CAN2_TX, SPI2_SCK, I2S2_CK and TMR1_CH1N.
53	PB14	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART3_RTS, SPI2_MISO, I2S2ext_SD, TMR1_CH2N, TMR12_CH1 and XMC_D0.
54	PB15	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI2_MOSI, I2S2_SD, TMR1_CH3N and TMR12_CH2.
55	PD8	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D13 and USART3_TX.
56	PD9	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D14 and USART3_RX.
57	PD10	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D15 and USART3_CK.
58	PD11	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_A16 and USART3_CTS.
59	PD12	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_A17, USART3_RTS and TMR4_CH1.
60	PD13	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_A18 and TMR4_CH2.
61	PD14	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D0 and TMR4_CH3.
62	PD15	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D1 and TMR4_CH4.
63	PC6	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART6_TX, I2S2_MCK, SDIO1_D6, TMR8_CH1, XMC_D1 and TMR3_CH1.
64	PC7	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART6_RX, I2S3_MCK, SDIO1_D7, TMR8_CH2 and TMR3_CH2.
65	PC8	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART6_CK, I2S4_MCK, SDIO1_D0, TMR8_CH3 and TMR3_CH3.
66	PC9	bidirectional	5 V-tolerant (FT) GPIO; alternate functions I2C3_SDA, SDIO1_D1, TMR8_CH4 and TMR3_CH4.
67	PA8	bidirectional	5 V-tolerant (FT) GPIO; alternate functions CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1.
68	PA9	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART1_TX, I2C3_SMBA and TMR1_CH2.
69	PA10	bidirectional	5 V-tolerant (FT) GPIO; alternate functions USART1_RX, TMR1_CH3 and I2S4_MCK.
70	PA11	bidirectional	Standard-level (TC) I/O; alternate functions USB_DM, USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4.
71	PA12	bidirectional	Standard-level (TC) I/O; alternate functions USB_DP, USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR.
72	PA13	bidirectional	5 V-tolerant (FT) GPIO; default function JTMS-SWDIO (SWJ debug data I/O).
73	NC	unconnected	Listed as not connected (未连接) in the pin definition table for LQFP100.
74	VSS_2	power_in	Ground pin; must be connected to the external ground system.
75	VDD_2	power_in	Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator.
76	PA14	bidirectional	5 V-tolerant (FT) GPIO; default function JTCK-SWCLK (SWJ debug clock).
77	PA15	bidirectional	5 V-tolerant (FT) GPIO; default function JTDI; alternate functions SPI3_NSS, I2S3_WS, SPI1_NSS, I2S1_WS, TMR2_CH1 and TMR2_ETR.
78	PC10	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART4_TX, SDIO1_D2, USART3_TX, SPI3_SCK and I2S3_CK.
79	PC11	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART4_RX, SDIO1_D3, USART3_RX, SPI3_MISO, I2S3ext_SD and XMC_D2.
80	PC12	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART5_TX, SDIO1_CK, USART3_CK, SPI3_MOSI, I2S3_SD and XMC_D3.
81	PD0	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D2 and CAN1_RX.
82	PD1	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_D3 and CAN1_TX.
83	PD2	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART5_RX, SDIO1_CMD, TMR3_ETR and XMC_NWE.
84	PD3	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_CLK and USART2_CTS.
85	PD4	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_NOE and USART2_RTS.
86	PD5	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_NWE and USART2_TX.
87	PD6	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_NWAIT and USART2_RX.
88	PD7	bidirectional	5 V-tolerant (FT) GPIO; alternate functions XMC_NE1, XMC_NCE2 and USART2_CK.
89	PB3	bidirectional	5 V-tolerant (FT) GPIO; default function JTDO (also TRACESWO); alternate functions SPI3_SCK, I2S3_CK, UART7_RX, SPI1_SCK, I2S1_CK and TMR2_CH2.
90	PB4	bidirectional	5 V-tolerant (FT) GPIO; default function NJTRST; alternate functions SPI3_MISO, I2S3ext_SD, SPI1_MISO, I2C3_SDA, UART7_TX and TMR3_CH1.
91	PB5	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SPI3_MOSI, I2S3_SD, I2C1_SMBA, SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2.
92	PB6	bidirectional	5 V-tolerant (FT) GPIO; alternate functions I2C1_SCL, SPIM_IO3, TMR4_CH1, USART1_TX, I2S1_MCK, SPI4_NSS, I2S4_WS and CAN2_TX.
93	PB7	bidirectional	5 V-tolerant (FT) GPIO; alternate functions I2C1_SDA, XMC_NADV, SPIM_IO2, TMR4_CH2, USART1_RX, SPI4_SCK and I2S4_CK.
94	BOOT0	input	Boot mode select input; its weak pull-down (RPD 60 to 100 kΩ) cannot be disabled.
95	PB8	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SDIO1_D4, TMR4_CH3, TMR10_CH1, UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX.
96	PB9	bidirectional	5 V-tolerant (FT) GPIO; alternate functions SDIO1_D5, TMR4_CH4, TMR11_CH1, UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX.
97	PE0	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART8_RX, XMC_NBL0 and TMR4_ETR.
98	PE1	bidirectional	5 V-tolerant (FT) GPIO; alternate functions UART8_TX and XMC_NBL1.
99	VSS_3	power_in	Ground pin; must be connected to the external ground system.
100	VDD_3	power_in	Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator; the 4.7 µF decoupling capacitor in the power scheme must be connected to VDD3.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range, supply and I/O pins (features summary)		2.6		3.6	V	供电和I/O引脚	1
Clock frequency in data transfer mode (SD/MMC)	fPP	0		48	MHz	CL ≤ 30 pF	77
Clock low time	tW(CKL)	32			ns	CL ≤ 30 pF	77
Clock high time	tW(CKH)	30			ns	CL ≤ 30 pF	77
Clock rise time	tr			4	ns	CL ≤ 30 pF	77
Clock fall time	tf			5	ns	CL ≤ 30 pF	77
Clock setup time, CMD and D inputs referenced to CK	tISU	2			ns	CL ≤ 30 pF	77
Clock hold time, CMD and D inputs referenced to CK	tIH	0			ns	CL ≤ 30 pF	77
Output valid time, MMC and SD high-speed mode, CMD and D referenced to CK	tOV			6	ns	CL ≤ 30 pF	77
Output hold time, MMC and SD high-speed mode, CMD and D referenced to CK	tOH	0			ns	CL ≤ 30 pF	77
Output valid default time, SD default mode, CMD and D referenced to CK	tOVD			7	ns	CL ≤ 30 pF	77
Output hold default time, SD default mode, CMD and D referenced to CK	tOHD	0.5			ns	CL ≤ 30 pF	77
USB transceiver startup time	tSTARTUP			1	μs		78
USB operating voltage	VDD	3		3.6	V		78
Differential input sensitivity	VDI	0.2			V	I (USB_DP，USB_DM)	78
Differential common-mode range	VCM	0.8		2.5	V	包含VDI范围	78
Single-ended receiver threshold	VSE	1.3		2	V		78
Static output low level	VOL			0.3	V	1.24 kΩ的RL接至3.6 V	78
Static output high level	VOH	2.8		3.6	V	15 kΩ的RL接至VSS	78
USB_DP internal pull-up resistor	RPU	0.97	1.24	1.58	kΩ	VIN = VSS	78
USB full-speed rise time	tr	4		20	ns	CL ≤ 50 pF	78
USB full-speed fall time	tf	4		20	ns	CL ≤ 50 pF	78
USB full-speed rise/fall time matching tr/tf	trfm	90		110	%		78
USB full-speed output signal crossover voltage	VCRS	1.3		2	V		78
ADC supply voltage	VDDA	2.6		3.6	V		79
ADC positive reference voltage	VREF+	2.6			V		79
Current on VDDA input pin	IDDA		380	445	μA		79
Current on VREF input pin	IVREF		200	220	μA		79
ADC clock frequency	fADC	0.6		28	MHz		79
ADC sampling rate	fS	0.05		2	MHz		79
External trigger frequency	fTRIG			1.65	MHz	fADC = 28 MHz	79
External trigger frequency	fTRIG			17	1/fADC		79
ADC conversion voltage range	VAIN	0			V	VSSA 或 VREF- 连接到地	79
Injected trigger conversion latency	tlat			107	ns	fADC = 28 MHz	79
Injected trigger conversion latency	tlat			3	1/fADC		79
Regular trigger conversion latency	tlatr			71.4	μs	fADC = 28 MHz	79
Regular trigger conversion latency	tlatr			2	1/fADC		79
Sampling time	tS	0.053		8.55	μs	fADC = 28 MHz	79
Sampling time	tS	1.5		239.5	1/fADC		79
Total conversion time including sampling	tCONV	0.5		9	μs	fADC = 28 MHz	79

CAD (KiCad official)

Symbol: AT32F403AVCT7
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: at32f403avct7-etched.step / at32f403avct7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f403avct7.step / at32f403avct7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (96 pp, sha256 602689c1ae94c051, retrieved 2026-10-19, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AT32F403AVCT7

**ARTERY** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

AT32F403AVCT7 from ARTERY, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI4_SCK/I2S4_CK, XMC_A23 and TRACECK. |
| 2 | PE3 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_A19 and TRACED0. |
| 3 | PE4 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI4_NSS/I2S4_WS, XMC_A20 and TRACED1. |
| 4 | PE5 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI4_MISO, XMC_A21, TRACED2 and TMR9_CH1. |
| 5 | PE6 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI4_MOSI/I2S4_SD, XMC_A22, TRACED3 and TMR9_CH2. |
| 6 | VBAT | power_in | Backup supply, 1.8 V to 3.6 V, powering the RTC, the 32 kHz oscillator and the backup registers when VDD is off. |
| 7 | PC13/TAMPER-RTC | bidirectional | Standard-level (TC) I/O with TAMPER-RTC function; supplied through a power switch limited to 3 mA, so as an output it is limited to medium drive, 30 pF maximum load, and must not source current (e.g. LEDs). |
| 8 | PC14/OSC32_IN | bidirectional | Standard-level (TC) I/O with OSC32_IN function; same 3 mA power-switch limit as PC13 applies when used as output. |
| 9 | PC15/OSC32_OUT | bidirectional | Standard-level (TC) I/O with OSC32_OUT function; same 3 mA power-switch limit as PC13 applies when used as output. |
| 10 | VSS_5 | power_in | Ground pin; must be connected to the external ground system. |
| 11 | VDD_5 | power_in | Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator. |
| 12 | OSC_IN | input | HSE oscillator input for a 4 to 25 MHz crystal/resonator or external user clock. |
| 13 | OSC_OUT | output | HSE oscillator output for the 4 to 25 MHz crystal/resonator. |
| 14 | NRST | bidirectional | Active-low reset pin with an internal pull-up (RPU 30 to 50 kΩ) that cannot be disconnected. |
| 15 | PC0 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN10 and SDIO2_D0. |
| 16 | PC1 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN11 and SDIO2_D1. |
| 17 | PC2 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN12, SDIO2_D2, UART8_TX and XMC_NWE. |
| 18 | PC3 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN13, SDIO2_D3, XMC_A0 and UART8_RX. |
| 19 | VSSA | power_in | Analog ground for the ADC and DAC; must be connected to VSS. |
| 20 | VREF- | power_in | Negative reference voltage input for the ADC and DAC; VREF- is included in the 50 mV maximum ground-difference limit. |
| 21 | VREF+ | power_in | Positive reference voltage input for the ADC and DAC, from 2.6 V up to VDDA (may be tied to VDDA). |
| 22 | VDDA | power_in | Analog supply, 2.6 V to 3.6 V, for the ADC and DAC; must be connected to VDD (up to 300 mV difference allowed). |
| 23 | PA0-WKUP | bidirectional | Standard-level (TC) I/O; wake-up input WKUP; alternate functions ADC123_IN0, USART2_CTS, TMR2_CH1, TMR2_ETR, TMR5_CH1, TMR8_ETR and UART4_TX. |
| 24 | PA1 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN1, USART2_RTS, TMR2_CH2, TMR5_CH2 and UART4_RX. |
| 25 | PA2 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN2, USART2_TX, TMR2_CH3, TMR5_CH3, TMR9_CH1, SDIO2_CK and XMC_D4. |
| 26 | PA3 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC123_IN3, USART2_RX, TMR2_CH4, TMR5_CH4, TMR9_CH2, I2S2_MCK, SDIO2_CMD and XMC_D5. |
| 27 | VSS_4 | power_in | Ground pin; must be connected to the external ground system. |
| 28 | VDD_4 | power_in | Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator. |
| 29 | PA4 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS, SDIO2_D4, USART6_TX, SPI3_NSS, I2S3_WS, SDIO2_D0 and XMC_D6. |
| 30 | PA5 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK, SDIO2_D5, USART6_RX, SDIO2_D1 and XMC_D7. |
| 31 | PA6 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN, TMR13_CH1, I2S2_MCK, SDIO2_D2 and TMR1_BKIN. |
| 32 | PA7 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN7, SPI1_MOSI, I2S1_SD, SDIO2_D7, TMR3_CH2, TMR8_CH1N, TMR14_CH1, SDIO2_D3 and TMR1_CH1N. |
| 33 | PC4 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN14, SDIO2_CK and XMC_NE4. |
| 34 | PC5 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN15, SDIO2_CMD and XMC_NOE. |
| 35 | PB0 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN8, I2S1_MCK, TMR3_CH3, TMR8_CH2N and TMR1_CH2N. |
| 36 | PB1 | bidirectional | 5 V-tolerant FTa I/O (not 5 V-tolerant in analog mode, where input must stay below VDD+0.3 V); alternate functions ADC12_IN9, SPIM_SCK, TMR3_CH4, TMR8_CH3N and TMR1_CH3N. |
| 37 | PB2/BOOT1 | bidirectional | 5 V-tolerant (FT) GPIO that also serves as the BOOT1 boot-mode configuration input. |
| 38 | PE7 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART7_RX, XMC_D4 and TMR1_ETR. |
| 39 | PE8 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART7_TX, XMC_D5 and TMR1_CH1N. |
| 40 | PE9 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D6 and TMR1_CH1. |
| 41 | PE10 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D7 and TMR1_CH2N. |
| 42 | PE11 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D8, SPI4_SCK, I2S4_CK and TMR1_CH2. |
| 43 | PE12 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D9, SPI4_NSS, I2S4_WS and TMR1_CH3N. |
| 44 | PE13 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D10, SPI4_MISO and TMR1_CH3. |
| 45 | PE14 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D11, SPI4_MOSI, I2S4_SD and TMR1_CH4. |
| 46 | PE15 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D12 and TMR1_BKIN. |
| 47 | PB10 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART3_TX, I2C2_SCL, I2S3_MCK, SPIM_IO0 and TMR2_CH3. |
| 48 | PB11 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART3_RX, I2C2_SDA, SPIM_IO1 and TMR2_CH4. |
| 49 | VSS_1 | power_in | Ground pin; must be connected to the external ground system. |
| 50 | VDD_1 | power_in | Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator. |
| 51 | PB12 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS, I2S2_WS, TMR1_BKIN and XMC_D13. |
| 52 | PB13 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART3_CTS, CAN2_TX, SPI2_SCK, I2S2_CK and TMR1_CH1N. |
| 53 | PB14 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART3_RTS, SPI2_MISO, I2S2ext_SD, TMR1_CH2N, TMR12_CH1 and XMC_D0. |
| 54 | PB15 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI2_MOSI, I2S2_SD, TMR1_CH3N and TMR12_CH2. |
| 55 | PD8 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D13 and USART3_TX. |
| 56 | PD9 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D14 and USART3_RX. |
| 57 | PD10 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D15 and USART3_CK. |
| 58 | PD11 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_A16 and USART3_CTS. |
| 59 | PD12 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_A17, USART3_RTS and TMR4_CH1. |
| 60 | PD13 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_A18 and TMR4_CH2. |
| 61 | PD14 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D0 and TMR4_CH3. |
| 62 | PD15 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D1 and TMR4_CH4. |
| 63 | PC6 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART6_TX, I2S2_MCK, SDIO1_D6, TMR8_CH1, XMC_D1 and TMR3_CH1. |
| 64 | PC7 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART6_RX, I2S3_MCK, SDIO1_D7, TMR8_CH2 and TMR3_CH2. |
| 65 | PC8 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART6_CK, I2S4_MCK, SDIO1_D0, TMR8_CH3 and TMR3_CH3. |
| 66 | PC9 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions I2C3_SDA, SDIO1_D1, TMR8_CH4 and TMR3_CH4. |
| 67 | PA8 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1. |
| 68 | PA9 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART1_TX, I2C3_SMBA and TMR1_CH2. |
| 69 | PA10 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions USART1_RX, TMR1_CH3 and I2S4_MCK. |
| 70 | PA11 | bidirectional | Standard-level (TC) I/O; alternate functions USB_DM, USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4. |
| 71 | PA12 | bidirectional | Standard-level (TC) I/O; alternate functions USB_DP, USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR. |
| 72 | PA13 | bidirectional | 5 V-tolerant (FT) GPIO; default function JTMS-SWDIO (SWJ debug data I/O). |
| 73 | NC | unconnected | Listed as not connected (未连接) in the pin definition table for LQFP100. |
| 74 | VSS_2 | power_in | Ground pin; must be connected to the external ground system. |
| 75 | VDD_2 | power_in | Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator. |
| 76 | PA14 | bidirectional | 5 V-tolerant (FT) GPIO; default function JTCK-SWCLK (SWJ debug clock). |
| 77 | PA15 | bidirectional | 5 V-tolerant (FT) GPIO; default function JTDI; alternate functions SPI3_NSS, I2S3_WS, SPI1_NSS, I2S1_WS, TMR2_CH1 and TMR2_ETR. |
| 78 | PC10 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART4_TX, SDIO1_D2, USART3_TX, SPI3_SCK and I2S3_CK. |
| 79 | PC11 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART4_RX, SDIO1_D3, USART3_RX, SPI3_MISO, I2S3ext_SD and XMC_D2. |
| 80 | PC12 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART5_TX, SDIO1_CK, USART3_CK, SPI3_MOSI, I2S3_SD and XMC_D3. |
| 81 | PD0 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D2 and CAN1_RX. |
| 82 | PD1 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_D3 and CAN1_TX. |
| 83 | PD2 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART5_RX, SDIO1_CMD, TMR3_ETR and XMC_NWE. |
| 84 | PD3 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_CLK and USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_NOE and USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_NWE and USART2_TX. |
| 87 | PD6 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_NWAIT and USART2_RX. |
| 88 | PD7 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions XMC_NE1, XMC_NCE2 and USART2_CK. |
| 89 | PB3 | bidirectional | 5 V-tolerant (FT) GPIO; default function JTDO (also TRACESWO); alternate functions SPI3_SCK, I2S3_CK, UART7_RX, SPI1_SCK, I2S1_CK and TMR2_CH2. |
| 90 | PB4 | bidirectional | 5 V-tolerant (FT) GPIO; default function NJTRST; alternate functions SPI3_MISO, I2S3ext_SD, SPI1_MISO, I2C3_SDA, UART7_TX and TMR3_CH1. |
| 91 | PB5 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SPI3_MOSI, I2S3_SD, I2C1_SMBA, SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2. |
| 92 | PB6 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions I2C1_SCL, SPIM_IO3, TMR4_CH1, USART1_TX, I2S1_MCK, SPI4_NSS, I2S4_WS and CAN2_TX. |
| 93 | PB7 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions I2C1_SDA, XMC_NADV, SPIM_IO2, TMR4_CH2, USART1_RX, SPI4_SCK and I2S4_CK. |
| 94 | BOOT0 | input | Boot mode select input; its weak pull-down (RPD 60 to 100 kΩ) cannot be disabled. |
| 95 | PB8 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SDIO1_D4, TMR4_CH3, TMR10_CH1, UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX. |
| 96 | PB9 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions SDIO1_D5, TMR4_CH4, TMR11_CH1, UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX. |
| 97 | PE0 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART8_RX, XMC_NBL0 and TMR4_ETR. |
| 98 | PE1 | bidirectional | 5 V-tolerant (FT) GPIO; alternate functions UART8_TX and XMC_NBL1. |
| 99 | VSS_3 | power_in | Ground pin; must be connected to the external ground system. |
| 100 | VDD_3 | power_in | Power supply pin, 2.6 V to 3.6 V, for I/O pins and the internal regulator; the 4.7 µF decoupling capacitor in the power scheme must be connected to VDD3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range, supply and I/O pins (features summary) |  | 2.6 |  | 3.6 | V | 供电和I/O引脚 | 1 |
| Clock frequency in data transfer mode (SD/MMC) | fPP | 0 |  | 48 | MHz | CL ≤ 30 pF | 77 |
| Clock low time | tW(CKL) | 32 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock high time | tW(CKH) | 30 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock rise time | tr |  |  | 4 | ns | CL ≤ 30 pF | 77 |
| Clock fall time | tf |  |  | 5 | ns | CL ≤ 30 pF | 77 |
| Clock setup time, CMD and D inputs referenced to CK | tISU | 2 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock hold time, CMD and D inputs referenced to CK | tIH | 0 |  |  | ns | CL ≤ 30 pF | 77 |
| Output valid time, MMC and SD high-speed mode, CMD and D referenced to CK | tOV |  |  | 6 | ns | CL ≤ 30 pF | 77 |
| Output hold time, MMC and SD high-speed mode, CMD and D referenced to CK | tOH | 0 |  |  | ns | CL ≤ 30 pF | 77 |
| Output valid default time, SD default mode, CMD and D referenced to CK | tOVD |  |  | 7 | ns | CL ≤ 30 pF | 77 |
| Output hold default time, SD default mode, CMD and D referenced to CK | tOHD | 0.5 |  |  | ns | CL ≤ 30 pF | 77 |
| USB transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 78 |
| USB operating voltage | VDD | 3 |  | 3.6 | V |  | 78 |
| Differential input sensitivity | VDI | 0.2 |  |  | V | I (USB_DP，USB_DM) | 78 |
| Differential common-mode range | VCM | 0.8 |  | 2.5 | V | 包含VDI范围 | 78 |
| Single-ended receiver threshold | VSE | 1.3 |  | 2 | V |  | 78 |
| Static output low level | VOL |  |  | 0.3 | V | 1.24 kΩ的RL接至3.6 V | 78 |
| Static output high level | VOH | 2.8 |  | 3.6 | V | 15 kΩ的RL接至VSS | 78 |
| USB_DP internal pull-up resistor | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 78 |
| USB full-speed rise time | tr | 4 |  | 20 | ns | CL ≤ 50 pF | 78 |
| USB full-speed fall time | tf | 4 |  | 20 | ns | CL ≤ 50 pF | 78 |
| USB full-speed rise/fall time matching tr/tf | trfm | 90 |  | 110 | % |  | 78 |
| USB full-speed output signal crossover voltage | VCRS | 1.3 |  | 2 | V |  | 78 |
| ADC supply voltage | VDDA | 2.6 |  | 3.6 | V |  | 79 |
| ADC positive reference voltage | VREF+ | 2.6 |  |  | V |  | 79 |
| Current on VDDA input pin | IDDA |  | 380 | 445 | μA |  | 79 |
| Current on VREF input pin | IVREF |  | 200 | 220 | μA |  | 79 |
| ADC clock frequency | fADC | 0.6 |  | 28 | MHz |  | 79 |
| ADC sampling rate | fS | 0.05 |  | 2 | MHz |  | 79 |
| External trigger frequency | fTRIG |  |  | 1.65 | MHz | fADC = 28 MHz | 79 |
| External trigger frequency | fTRIG |  |  | 17 | 1/fADC |  | 79 |
| ADC conversion voltage range | VAIN | 0 |  |  | V | VSSA 或 VREF- 连接到地 | 79 |
| Injected trigger conversion latency | tlat |  |  | 107 | ns | fADC = 28 MHz | 79 |
| Injected trigger conversion latency | tlat |  |  | 3 | 1/fADC |  | 79 |
| Regular trigger conversion latency | tlatr |  |  | 71.4 | μs | fADC = 28 MHz | 79 |
| Regular trigger conversion latency | tlatr |  |  | 2 | 1/fADC |  | 79 |
| Sampling time | tS | 0.053 |  | 8.55 | μs | fADC = 28 MHz | 79 |
| Sampling time | tS | 1.5 |  | 239.5 | 1/fADC |  | 79 |
| Total conversion time including sampling | tCONV | 0.5 |  | 9 | μs | fADC = 28 MHz | 79 |

## CAD (KiCad official)

- Symbol: `AT32F403AVCT7`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `at32f403avct7-etched.step` / `at32f403avct7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f403avct7.step` / `at32f403avct7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ARTERY datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886679369629696) (96 pp, sha256 `602689c1ae94c051`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at32f403avct7-datasheet.pdf)