component
AT32F403ARGT7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAT32F403ARGT7
ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
AT32F403ARGT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply, 1.8 to 3.6 V, powers the RTC, the 32 kHz oscillator and the backup registers when VDD is off. |
| 2 | PC13/TAMPER-RTC | bidirectional | General-purpose I/O (standard level, not 5 V tolerant) also used as TAMPER-RTC; it is supplied through a power switch limited to 3 mA, so as an output it is limited to moderate drive, 30 pF maximum load and no LED current sourcing. |
| 3 | PC14/OSC32_IN | bidirectional | General-purpose I/O (standard level) that is OSC32_IN, the LSE 32.768 kHz crystal input, by default; same 3 mA power-switch and output limits as PC13. |
| 4 | PC15/OSC32_OUT | bidirectional | General-purpose I/O (standard level) that is OSC32_OUT, the LSE 32.768 kHz crystal output, by default; same 3 mA power-switch and output limits as PC13. |
| 5 | PD0/OSC_IN | bidirectional | Standard-level I/O that is OSC_IN, the HSE 4 to 25 MHz oscillator input, after reset; it can be remapped to PD0 by software. |
| 6 | PD1/OSC_OUT | bidirectional | Standard-level I/O that is OSC_OUT, the HSE oscillator output, after reset; it can be remapped to PD1 by software. |
| 7 | NRST | input | Active-low reset input with internal pull-up (RPU 30 to 50 kΩ); VIL max 0.8 V and VIH min 2 V, and the datasheet recommends a 0.1 µF filter capacitor. |
| 8 | PC0 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN10 and SDIO2_D0; in analog mode the input must stay below VDD + 0.3 V. |
| 9 | PC1 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN11 and SDIO2_D1; in analog mode the input must stay below VDD + 0.3 V. |
| 10 | PC2 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN12, SDIO2_D2, UART8_TX and XMC_NWE; in analog mode the input must stay below VDD + 0.3 V. |
| 11 | PC3 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN13, SDIO2_D3, XMC_A0 and UART8_RX; in analog mode the input must stay below VDD + 0.3 V. |
| 12 | VSSA | power_in | Analog ground for ADC and DAC; must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for ADC and DAC, 2.6 to 3.6 V; must be connected to VDD (up to 300 mV difference is allowed during power-up and operation). |
| 14 | PA0-WKUP | bidirectional | Standard-level I/O (TC, not 5 V tolerant) with ADC123_IN0, WKUP wake-up input, USART2_CTS and TMR2/TMR5/TMR8 functions. |
| 15 | PA1 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN1, USART2_RTS, TMR2_CH2 and TMR5_CH2. |
| 16 | PA2 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN2, USART2_TX, TMR2_CH3, TMR5_CH3, TMR9_CH1, SDIO2_CK and XMC_D4. |
| 17 | PA3 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC123_IN3, USART2_RX, TMR2_CH4, TMR5_CH4, TMR9_CH2, I2S2_MCK, SDIO2_CMD and XMC_D5. |
| 18 | VSS_4 | power_in | Ground for the digital I/O and core. |
| 19 | VDD_4 | power_in | Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V. |
| 20 | PA4 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS, USART6_TX, SPI3_NSS, I2S3_WS, SDIO2_D0 and XMC_D6. |
| 21 | PA5 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK, SDIO2_D5, USART6_RX, SDIO2_D1 and XMC_D7. |
| 22 | PA6 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN, TMR13_CH1, I2S2_MCK, SDIO2_D2 and TMR1_BKIN. |
| 23 | PA7 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN7, SPI1_MOSI, I2S1_SD, SDIO2_D7, TMR3_CH2, TMR8_CH1N, TMR14_CH1, SDIO2_D3 and TMR1_CH1N. |
| 24 | PC4 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN14, SDIO2_CK and XMC_NE4. |
| 25 | PC5 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN15, SDIO2_CMD and XMC_NOE. |
| 26 | PB0 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN8, I2S1_MCK, TMR3_CH3, TMR8_CH2N and TMR1_CH2N. |
| 27 | PB1 | bidirectional | 5 V tolerant I/O with analog function (FTa), usable as ADC12_IN9, SPIM_SCK, TMR3_CH4, TMR8_CH3N and TMR1_CH3N. |
| 28 | PB2/BOOT1 | bidirectional | 5 V tolerant general-purpose I/O (FT) that also serves as the BOOT1 boot-mode configuration input. |
| 29 | PB10 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART3_TX, I2C2_SCL, I2S3_MCK, SPIM_IO0 and TMR2_CH3. |
| 30 | PB11 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART3_RX, I2C2_SDA, SPIM_IO1 and TMR2_CH4. |
| 31 | VSS_1 | power_in | Ground for the digital I/O and core. |
| 32 | VDD_1 | power_in | Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS, I2S2_WS, TMR1_BKIN and XMC_D13. |
| 34 | PB13 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART3_CTS, CAN2_TX, SPI2_SCK, I2S2_CK and TMR1_CH1N. |
| 35 | PB14 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART3_RTS, SPI2_MISO, I2S2ext_SD, TMR1_CH2N, TMR12_CH1 and XMC_D0. |
| 36 | PB15 | bidirectional | 5 V tolerant general-purpose I/O (FT) with SPI2_MOSI, I2S2_SD, TMR1_CH3N and TMR12_CH2. |
| 37 | PC6 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART6_TX, I2S2_MCK, SDIO1_D6, TMR8_CH1, XMC_D1 and TMR3_CH1. |
| 38 | PC7 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART6_RX, I2S3_MCK, SDIO1_D7, TMR8_CH2 and TMR3_CH2. |
| 39 | PC8 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART6_CK, I2S4_MCK, SDIO1_D0, TMR8_CH3 and TMR3_CH3. |
| 40 | PC9 | bidirectional | 5 V tolerant general-purpose I/O (FT) with I2C3_SDA, SDIO1_D1, TMR8_CH4 and TMR3_CH4. |
| 41 | PA8 | bidirectional | 5 V tolerant general-purpose I/O (FT) with CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1. |
| 42 | PA9 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART1_TX, I2C3_SMBA and TMR1_CH2; PA9 is the default USART1_TX of the bootloader. |
| 43 | PA10 | bidirectional | 5 V tolerant general-purpose I/O (FT) with USART1_RX, TMR1_CH3 and I2S4_MCK; PA10 is the default USART1_RX of the bootloader. |
| 44 | PA11 | bidirectional | Standard-level I/O (TC, not 5 V tolerant) that is USB_DM by default, also USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4. |
| 45 | PA12 | bidirectional | Standard-level I/O (TC, not 5 V tolerant) that is USB_DP by default, also USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR. |
| 46 | PA13 | bidirectional | 5 V tolerant I/O (FT) that is the JTMS/SWDIO debug pin by default. |
| 47 | VSS_2 | power_in | Ground for the digital I/O and core. |
| 48 | VDD_2 | power_in | Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant I/O (FT) that is the JTCK/SWCLK debug pin by default. |
| 50 | PA15 | bidirectional | 5 V tolerant I/O (FT) that is the JTDI debug pin by default, also SPI3_NSS, I2S3_WS, SPI1_NSS, I2S1_WS, TMR2_CH1 and TMR2_ETR after remap. |
| 51 | PC10 | bidirectional | 5 V tolerant general-purpose I/O (FT) with UART4_TX, SDIO1_D2, USART3_TX, SPI3_SCK and I2S3_CK. |
| 52 | PC11 | bidirectional | 5 V tolerant general-purpose I/O (FT) with UART4_RX, SDIO1_D3, USART3_RX, SPI3_MISO, I2S3ext_SD and XMC_D2. |
| 53 | PC12 | bidirectional | 5 V tolerant general-purpose I/O (FT) with UART5_TX, SDIO1_CK, USART3_CK, SPI3_MOSI, I2S3_SD and XMC_D3. |
| 54 | PD2 | bidirectional | 5 V tolerant general-purpose I/O (FT) with UART5_RX, SDIO1_CMD, TMR3_ETR and XMC_NWE. |
| 55 | PB3 | bidirectional | 5 V tolerant I/O (FT) that is the JTDO/TRACESWO debug pin by default, also SPI3_SCK, I2S3_CK, UART7_RX, SPI1_SCK and TMR2_CH2. |
| 56 | PB4 | bidirectional | 5 V tolerant I/O (FT) that is the NJTRST debug pin by default, also SPI3_MISO, I2S3ext_SD, SPI1_MISO, I2C3_SDA, UART7_TX and TMR3_CH1. |
| 57 | PB5 | bidirectional | 5 V tolerant general-purpose I/O (FT) with SPI3_MOSI, I2S3_SD, I2C1_SMBA, SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2. |
| 58 | PB6 | bidirectional | 5 V tolerant general-purpose I/O (FT) with I2C1_SCL, SPIM_IO3, TMR4_CH1, USART1_TX, I2S1_MCK, SPI4_NSS, I2S4_WS and CAN2_TX. |
| 59 | PB7 | bidirectional | 5 V tolerant general-purpose I/O (FT) with I2C1_SDA, XMC_NADV, SPIM_IO2, TMR4_CH2, USART1_RX, SPI4_SCK and I2S4_CK. |
| 60 | BOOT0 | input | Boot-mode selection input that sets the start-up memory; it has an internal weak pull-down that cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V tolerant general-purpose I/O (FT) with SDIO1_D4, TMR4_CH3, TMR10_CH1, UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V tolerant general-purpose I/O (FT) with SDIO1_D5, TMR4_CH4, TMR11_CH1, UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX. |
| 63 | VSS_3 | power_in | Ground for the digital I/O and core. |
| 64 | VDD_3 | power_in | Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| SD/MMC data transfer clock frequency | fPP | 0 | 48 | MHz | CL ≤ 30 pF | 77 | |
| SD/MMC clock low time | tW(CKL) | 32 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock high time | tW(CKH) | 30 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock rise time | tr | 4 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock fall time | tf | 5 | ns | CL ≤ 30 pF | 77 | ||
| CMD, D input setup time (referenced to CK) | tISU | 2 | ns | CL ≤ 30 pF | 77 | ||
| CMD, D input hold time (referenced to CK) | tIH | 0 | ns | CL ≤ 30 pF | 77 | ||
| CMD, D output valid time, MMC and SD high-speed mode (referenced to CK) | tOV | 6 | ns | MMC和SD高速模式; CL ≤ 30 pF | 77 | ||
| CMD, D output hold time, MMC and SD high-speed mode (referenced to CK) | tOH | 0 | ns | MMC和SD高速模式; CL ≤ 30 pF | 77 | ||
| CMD, D output valid default time, SD default mode (referenced to CK) | tOVD | 7 | ns | SD默认模式; CL ≤ 30 pF | 77 | ||
| CMD, D output hold default time, SD default mode (referenced to CK) | tOHD | 0.5 | ns | SD默认模式; CL ≤ 30 pF | 77 | ||
| USB transceiver startup time | tSTARTUP | 1 | μs | 78 | |||
| USB operating voltage | VDD | 3 | 3.6 | V | 78 | ||
| Differential input sensitivity | VDI | 0.2 | V | I (USB_DP，USB_DM) | 78 | ||
| Differential common-mode range | VCM | 0.8 | 2.5 | V | 包含VDI范围 | 78 | |
| Single-ended receiver threshold | VSE | 1.3 | 2 | V | 78 | ||
| Static output low level | VOL | 0.3 | V | 1.24 kΩ的RL接至3.6 V(4) | 78 | ||
| Static output high level | VOH | 2.8 | 3.6 | V | 15 kΩ的RL接至VSS(4) | 78 | |
| USB_DP internal pull-up resistance | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 78 |
| USB full-speed rise time | tr | 4 | 20 | ns | CL ≤ 50 pF | 78 | |
| USB full-speed fall time | tf | 4 | 20 | ns | CL ≤ 50 pF | 78 | |
| USB rise/fall time matching (tr/tf) | trfm | 90 | 110 | % | 78 | ||
| Output signal crossover voltage | VCRS | 1.3 | 2 | V | 78 | ||
| ADC supply voltage | VDDA | 2.6 | 3.6 | V | 79 | ||
| ADC positive reference voltage | VREF+ | 2.6 | V | 79 | |||
| Current into VDDA input pin | IDDA | 445 | μA | 79 | |||
| Current into VREF input pin | IVREF | 220 | μA | 79 | |||
| ADC clock frequency | fADC | 0.6 | 28 | MHz | 79 | ||
| ADC sampling rate | fS | 0.05 | 2 | MHz | 79 | ||
| External trigger frequency | fTRIG | 1.65 | MHz | fADC = 28 MHz | 79 | ||
| External trigger frequency (in 1/fADC) | fTRIG | 17 | 1/fADC | 79 | |||
| ADC conversion voltage range | VAIN | 0 | V | 79 | |||
| Injected trigger conversion latency | tlat | 107 | ns | fADC = 28 MHz | 79 | ||
| Injected trigger conversion latency (in 1/fADC) | tlat | 3 | 1/fADC | 79 | |||
| Regular trigger conversion latency | tlatr | 71.4 | μs | fADC = 28 MHz | 79 | ||
| Regular trigger conversion latency (in 1/fADC) | tlatr | 2 | 1/fADC | 79 | |||
| ADC sampling time | tS | 0.053 | 8.55 | μs | fADC = 28 MHz | 79 | |
| ADC sampling time (in 1/fADC) | tS | 1.5 | 239.5 | 1/fADC | 79 | ||
| ADC total conversion time incl. sampling | tCONV | 0.5 | 9 | μs | fADC = 28 MHz | 79 | |
| ADC total conversion time incl. sampling (in 1/fADC) | tCONV | 14 | 252 | 1/fADC | 79 |
CAD (KiCad official)
- Symbol:
AT32F403ARGT7 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
at32f403argt7-etched.step/at32f403argt7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f403argt7.step/at32f403argt7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (96 pp, sha256
602689c1ae94c051, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).