# AT32F403ARCT7

**ARTERY** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

AT32F403ARCT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply input at 1.8 to 3.6 V that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off. |
| 2 | PC13/TAMPER-RTC | bidirectional | Standard-level I/O (TC) with TAMPER-RTC function, powered through the VBAT power switch, which limits it to 3 mA so it may only be used as a moderate-drive output with max 30 pF load and not as a current source. |
| 3 | PC14/OSC32_IN | bidirectional | Standard-level I/O (TC) that serves as the OSC32_IN input of the 32.768 kHz LSE crystal, with the same 3 mA power-switch limit when used as an output. |
| 4 | PC15/OSC32_OUT | bidirectional | Standard-level I/O (TC) that serves as the OSC32_OUT output of the 32.768 kHz LSE crystal, with the same 3 mA power-switch limit when used as an output. |
| 5 | PD0/OSC_IN | bidirectional | After reset this 5 V-tolerant pin (FT) is the HSE oscillator input (4 to 25 MHz crystal), and software may reconfigure it as PD0 on LQFP64. |
| 6 | PD1/OSC_OUT | bidirectional | After reset this 5 V-tolerant pin (FT) is the HSE oscillator output, and software may reconfigure it as PD1 on LQFP64. |
| 7 | NRST | input | Active-low reset input with internal pull-up of about 40 kΩ (30 to 50 kΩ) and 500 mV Schmitt hysteresis, which requires the external reset protection shown in the datasheet. |
| 8 | PC0 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN10 and SDIO2_D0 functions; in analog mode the input must stay below VDD + 0.3 V. |
| 9 | PC1 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN11 and SDIO2_D1 functions; in analog mode the input must stay below VDD + 0.3 V. |
| 10 | PC2 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN12 and SDIO2_D2 functions; remap options include UART8_TX and XMC_NWE. |
| 11 | PC3 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN13, SDIO2_D3 and XMC_A0 functions; remap option is UART8_RX. |
| 12 | VSSA | power_in | Analog ground, which must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC and DAC at 2.6 to 3.6 V, which must be connected to VDD (at most 300 mV difference during operation). |
| 14 | PA0/WKUP | bidirectional | Standard-level I/O (TC) with ADC123_IN0, WKUP wake-up, USART2_CTS, TMR2_CH1/TMR2_ETR, TMR5_CH1 and TMR8_ETR functions; remap option is UART4_TX. |
| 15 | PA1 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN1, USART2_RTS, TMR2_CH2 and TMR5_CH2 functions; remap option is UART4_RX. |
| 16 | PA2 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN2, USART2_TX, TMR2_CH3, TMR5_CH3 and TMR9_CH1 functions. |
| 17 | PA3 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC123_IN3, USART2_RX, TMR2_CH4, TMR5_CH4 and TMR9_CH2 functions. |
| 18 | VSS_4 | power_in | Ground pin for the I/O and digital supply domain. |
| 19 | VDD_4 | power_in | I/O and internal regulator supply at 2.6 to 3.6 V. |
| 20 | PA4 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS and SDIO2_D4 functions. |
| 21 | PA5 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with DAC_OUT2, ADC12_IN5, SPI1_SCK, I2S1_CK and SDIO2_D5 functions. |
| 22 | PA6 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN and TMR13_CH1 functions. |
| 23 | PA7 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN7, SPI1_MOSI, I2S1_SD, SDIO2_D7, TMR3_CH2, TMR8_CH1N and TMR14_CH1 functions. |
| 24 | PC4 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN14, SDIO2_CK and XMC_NE4 functions. |
| 25 | PC5 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN15, SDIO2_CMD and XMC_NOE functions. |
| 26 | PB0 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN8, I2S1_MCK, TMR3_CH3 and TMR8_CH2N functions; remap option is TMR1_CH2N. |
| 27 | PB1 | bidirectional | 5 V-tolerant analog-capable I/O (FTa) with ADC12_IN9, SPIM_SCK, TMR3_CH4 and TMR8_CH3N functions; remap option is TMR1_CH3N. |
| 28 | PB2/BOOT1 | bidirectional | 5 V-tolerant I/O (FT) that is also the BOOT1 boot-mode pin. |
| 29 | PB10 | bidirectional | 5 V-tolerant I/O (FT) with USART3_TX and I2C2_SCL functions; remap options include I2S3_MCK, SPIM_IO0 and TMR2_CH3. |
| 30 | PB11 | bidirectional | 5 V-tolerant I/O (FT) with USART3_RX and I2C2_SDA functions; remap options include SPIM_IO1 and TMR2_CH4. |
| 31 | VSS_1 | power_in | Ground pin for the I/O and digital supply domain. |
| 32 | VDD_1 | power_in | I/O and internal regulator supply at 2.6 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V-tolerant I/O (FT) with USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS, I2S2_WS and TMR1_BKIN functions; remap option is XMC_D13. |
| 34 | PB13 | bidirectional | 5 V-tolerant I/O (FT) with USART3_CTS, CAN2_TX, SPI2_SCK, I2S2_CK and TMR1_CH1N functions. |
| 35 | PB14 | bidirectional | 5 V-tolerant I/O (FT) with USART3_RTS, SPI2_MISO, I2S2ext_SD, TMR1_CH2N and TMR12_CH1 functions; remap option is XMC_D0. |
| 36 | PB15 | bidirectional | 5 V-tolerant I/O (FT) with SPI2_MOSI, I2S2_SD, TMR1_CH3N and TMR12_CH2 functions. |
| 37 | PC6 | bidirectional | 5 V-tolerant I/O (FT) with USART6_TX, I2S2_MCK, SDIO1_D6 and TMR8_CH1 functions; remap options include XMC_D1 and TMR3_CH1. |
| 38 | PC7 | bidirectional | 5 V-tolerant I/O (FT) with USART6_RX, I2S3_MCK, SDIO1_D7 and TMR8_CH2 functions; remap option is TMR3_CH2. |
| 39 | PC8 | bidirectional | 5 V-tolerant I/O (FT) with USART6_CK, I2S4_MCK, SDIO1_D0 and TMR8_CH3 functions; remap option is TMR3_CH3. |
| 40 | PC9 | bidirectional | 5 V-tolerant I/O (FT) with I2C3_SDA, SDIO1_D1 and TMR8_CH4 functions; remap option is TMR3_CH4. |
| 41 | PA8 | bidirectional | 5 V-tolerant I/O (FT) with CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1 functions. |
| 42 | PA9 | bidirectional | 5 V-tolerant I/O (FT) with USART1_TX, I2C3_SMBA and TMR1_CH2 functions. |
| 43 | PA10 | bidirectional | 5 V-tolerant I/O (FT) with USART1_RX and TMR1_CH3 functions; remap option is I2S4_MCK. |
| 44 | PA11 | bidirectional | Standard-level I/O (TC) that is the USB_DM full-speed data line, also with USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4 functions. |
| 45 | PA12 | bidirectional | Standard-level I/O (TC) that is the USB_DP full-speed data line with internal pull-up of 0.97 to 1.58 kΩ, also with USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR functions. |
| 46 | PA13 | bidirectional | 5 V-tolerant I/O (FT) whose default function is the JTMS-SWDIO serial-wire debug data pin. |
| 47 | VSS_2 | power_in | Ground pin for the I/O and digital supply domain. |
| 48 | VDD_2 | power_in | I/O and internal regulator supply at 2.6 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V-tolerant I/O (FT) whose default function is the JTCK-SWCLK serial-wire debug clock pin. |
| 50 | PA15 | bidirectional | 5 V-tolerant I/O (FT) whose default function is JTDI; alternate functions include SPI3_NSS and I2S3_WS. |
| 51 | PC10 | bidirectional | 5 V-tolerant I/O (FT) with UART4_TX and SDIO1_D2 functions; remap options include USART3_TX, SPI3_SCK and I2S3_CK. |
| 52 | PC11 | bidirectional | 5 V-tolerant I/O (FT) with UART4_RX and SDIO1_D3 functions; remap options include USART3_RX, SPI3_MISO, I2S3ext_SD and XMC_D2. |
| 53 | PC12 | bidirectional | 5 V-tolerant I/O (FT) with UART5_TX and SDIO1_CK functions; remap options include USART3_CK, SPI3_MOSI, I2S3_SD and XMC_D3. |
| 54 | PD2 | bidirectional | 5 V-tolerant I/O (FT) with UART5_RX, SDIO1_CMD and TMR3_ETR functions; remap option is XMC_NWE. |
| 55 | PB3 | bidirectional | 5 V-tolerant I/O (FT) whose default function is the JTDO serial-wire trace output; alternate functions include SPI3_SCK and I2S3_CK. |
| 56 | PB4 | bidirectional | 5 V-tolerant I/O (FT) whose default function is NJTRST (JTAG test reset); alternate functions include SPI3_MISO and I2S3ext_SD. |
| 57 | PB5 | bidirectional | 5 V-tolerant I/O (FT) with SPI3_MOSI, I2S3_SD and I2C1_SMBA functions; remap options include SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2. |
| 58 | PB6 | bidirectional | 5 V-tolerant I/O (FT) with I2C1_SCL, SPIM_IO3 and TMR4_CH1 functions; remap options include USART1_TX, I2S1_MCK, SPI4_NSS, I2S4_WS and CAN2_TX. |
| 59 | PB7 | bidirectional | 5 V-tolerant I/O (FT) with I2C1_SDA, XMC_NADV, SPIM_IO2 and TMR4_CH2 functions; remap options include USART1_RX, SPI4_SCK and I2S4_CK. |
| 60 | BOOT0 | input | Boot-mode select input whose internal weak pull-down cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V-tolerant I/O (FT) with SDIO1_D4, TMR4_CH3 and TMR10_CH1 functions; remap options include UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V-tolerant I/O (FT) with SDIO1_D5, TMR4_CH4 and TMR11_CH1 functions; remap options include UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX. |
| 63 | VSS_3 | power_in | Ground pin for the I/O and digital supply domain. |
| 64 | VDD_3 | power_in | I/O and internal regulator supply at 2.6 to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Clock frequency in data transfer mode | fPP | 0 |  | 48 | MHz | CL ≤ 30 pF | 77 |
| Clock low time | tW(CKL) | 32 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock high time | tW(CKH) | 30 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock rise time | tr |  |  | 4 | ns | CL ≤ 30 pF | 77 |
| Clock fall time | tf |  |  | 5 | ns | CL ≤ 30 pF | 77 |
| Clock setup time, CMD/D inputs referenced to CK | tISU | 2 |  |  | ns | CL ≤ 30 pF | 77 |
| Clock hold time, CMD/D inputs referenced to CK | tIH | 0 |  |  | ns | CL ≤ 30 pF | 77 |
| Output valid time, CMD/D outputs (MMC and SD high speed) | tOV |  |  | 6 | ns | CL ≤ 30 pF | 77 |
| Output hold time, CMD/D outputs (MMC and SD high speed) | tOH | 0 |  |  | ns | CL ≤ 30 pF | 77 |
| Output valid default time, CMD/D outputs (SD default mode) | tOVD |  |  | 7 | ns | CL ≤ 30 pF | 77 |
| Output hold default time, CMD/D outputs (SD default mode) | tOHD | 0.5 |  |  | ns | CL ≤ 30 pF | 77 |
| USB transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 78 |
| USB operating voltage | VDD | 3 |  | 3.6 | V |  | 78 |
| Differential input sensitivity | VDI | 0.2 |  |  |  | I (USB_DP, USB_DM) | 78 |
| Differential common-mode range | VCM | 0.8 |  | 2.5 | V | 包含VDI范围 | 78 |
| Single-ended receiver threshold | VSE | 1.3 |  | 2 |  |  | 78 |
| Static output low level | VOL |  |  | 0.3 | V | 1.24 kΩ的RL接至3.6 V | 78 |
| Static output high level | VOH | 2.8 |  | 3.6 | V | 15 kΩ的RL接至VSS | 78 |
| USB_DP internal pull-up resistance | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 78 |
| Rise time | tr | 4 |  | 20 | ns | CL ≤ 50 pF | 78 |
| Fall time | tf | 4 |  | 20 | ns | CL ≤ 50 pF | 78 |
| Rise/fall time matching tr/tf | trfm | 90 |  | 110 | % |  | 78 |
| Output signal crossover voltage | VCRS | 1.3 |  | 2 | V |  | 78 |
| ADC supply voltage | VDDA | 2.6 |  | 3.6 | V |  | 79 |
| ADC positive reference voltage | VREF+ | 2.6 |  |  | V |  | 79 |
| Current on VDDA input pin | IDDA |  | 380 | 445 | μA |  | 79 |
| Current on VREF input pin | IVREF |  | 200 | 220 | μA |  | 79 |
| ADC clock frequency | fADC | 0.6 |  | 28 | MHz |  | 79 |
| ADC sampling rate | fS | 0.05 |  | 2 | MHz |  | 79 |
| External trigger frequency | fTRIG |  |  | 1.65 | MHz | fADC = 28 MHz | 79 |
| External trigger frequency | fTRIG |  |  | 17 | 1/fADC |  | 79 |
| Conversion voltage range | VAIN | 0 |  |  | V | VSSA 或 VREF- 连接到地 | 79 |
| Injected trigger conversion latency | tlat |  |  | 107 | ns | fADC = 28 MHz | 79 |
| Injected trigger conversion latency | tlat |  |  | 3 | 1/fADC |  | 79 |
| Regular trigger conversion latency | tlatr |  |  | 71.4 | μs | fADC = 28 MHz | 79 |
| Regular trigger conversion latency | tlatr |  |  | 2 | 1/fADC |  | 79 |
| Sampling time | tS | 0.053 |  | 8.55 | μs | fADC = 28 MHz | 79 |
| Sampling time | tS | 1.5 |  | 239.5 | 1/fADC |  | 79 |
| Total conversion time (including sampling) | tCONV | 0.5 |  | 9 | μs | fADC = 28 MHz | 79 |
| Total conversion time (including sampling) | tCONV | 14 |  | 252 | 1/fADC |  | 79 |
| Supply and I/O pin voltage (feature summary) |  | 2.6 |  | 3.6 | V |  | 1 |

## CAD (KiCad official)

- Symbol: `AT32F403ARCT7`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `at32f403arct7-etched.step` / `at32f403arct7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f403arct7.step` / `at32f403arct7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ARTERY datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893564943650816) (96 pp, sha256 `602689c1ae94c051`, retrieved 2026-10-16, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at32f403arct7-datasheet.pdf)