component

AT32F403ACGT7

Public Made by Adom

by adom

ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat32f403acgt7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers at32f403acgt7: viewers · Ray 8d ago
at32f403acgt7-etched.glb Publish 0.1.0 · Ray 8d ago
at32f403acgt7-etched.step at32f403acgt7: factory component page (tier=lcsc) · Ray 8d ago
at32f403acgt7-hero.glb at32f403acgt7: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
at32f403acgt7-hero.overlay.json Publish 0.1.0 · Ray 8d ago
at32f403acgt7.glb Publish 0.1.0 · Ray 8d ago
at32f403acgt7.kicad_mod Publish 0.1.0 · Ray 8d ago
at32f403acgt7.kicad_sym Publish 0.1.0 · Ray 8d ago
at32f403acgt7.lbr Publish 0.1.0 · Ray 8d ago
at32f403acgt7.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

AT32F403ACGT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

AT32F403ACGT7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply, 1.8 to 3.6 V, powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off.
2 PC13/TAMPER-RTC bidirectional Standard-level (TC) I/O also used as TAMPER-RTC; it is fed through a power switch limited to 3 mA, so as an output it is restricted to medium drive with a maximum 30 pF load and cannot source LEDs.
3 PC14/OSC32_IN bidirectional Standard-level (TC) I/O multiplexed with the LSE 32.768 kHz oscillator input OSC32_IN, with the same 3 mA power-switch limit as PC13.
4 PC15/OSC32_OUT bidirectional Standard-level (TC) I/O multiplexed with the LSE oscillator output OSC32_OUT, with the same 3 mA power-switch limit as PC13.
5 PD0/OSC_IN bidirectional Standard-level (TC) pin that defaults to the HSE oscillator input OSC_IN (4 to 25 MHz crystal) after reset and can be remapped to PD0 by software.
6 PD1/OSC_OUT bidirectional Standard-level (TC) pin that defaults to the HSE oscillator output OSC_OUT after reset and can be remapped to PD1 by software.
7 NRST input Active-low reset input with an internal pull-up of 30 to 50 kΩ, with VIL maximum 0.8 V and VIH minimum 2 V.
8 VSSA power_in Analog ground for the ADC and DAC; must be connected to VSS.
9 VDDA power_in Analog supply for the ADC and DAC, 2.6 to 3.6 V; must be connected to VDD (at most 300 mV difference during power-up and operation).
10 PA0-WKUP bidirectional Standard-level (TC) I/O with ADC123_IN0 analog input and the WKUP wake-up function, also USART2_CTS, TMR2 and UART4_TX alternates.
11 PA1 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC123_IN1 and USART2_RTS alternates.
12 PA2 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC123_IN2, USART2_TX and TMR alternates.
13 PA3 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC123_IN3, USART2_RX and TMR alternates.
14 PA4 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; DAC_OUT1 and ADC12_IN4 analog functions, USART2_CK and SPI1_NSS alternates.
15 PA5 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; DAC_OUT2 and ADC12_IN5 analog functions, SPI1_SCK alternate.
16 PA6 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC12_IN6, SPI1_MISO and TMR3/TMR8/TMR13 alternates.
17 PA7 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC12_IN7, SPI1_MOSI and TMR3/TMR8/TMR14 alternates.
18 PB0 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC12_IN8, I2S1_MCK and TMR3/TMR8 alternates.
19 PB1 bidirectional 5 V-tolerant I/O (FTa) when configured as input, but not 5 V-tolerant in analog mode where the input must stay below VDD + 0.3 V; ADC12_IN9, SPIM_SCK and TMR3/TMR8 alternates.
20 PB2/BOOT1 bidirectional 5 V-tolerant general-purpose I/O (FT) shared with the BOOT1 boot-configuration function.
21 PB10 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART3_TX and I2C2_SCL alternates; remap options include I2S3_MCK, SPIM_IO0 and TMR2_CH3.
22 PB11 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART3_RX and I2C2_SDA alternates; remap options include SPIM_IO1 and TMR2_CH4.
23 VSS_1 power_in Digital ground for the I/O and logic.
24 VDD_1 power_in Digital supply for I/O pins and internal regulator, 2.6 to 3.6 V.
25 PB12 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART3_CK, CAN2_RX, SPI2_NSS, I2S2_WS and TMR1_BKIN alternates; remap option XMC_D13.
26 PB13 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART3_CTS, CAN2_TX, SPI2_SCK, I2S2_CK and TMR1_CH1N alternates.
27 PB14 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART3_RTS, SPI2_MISO, I2S2ext_SD and TMR1/TMR12 alternates; remap option XMC_D0.
28 PB15 bidirectional 5 V-tolerant general-purpose I/O (FT) with SPI2_MOSI, I2S2_SD, TMR1_CH3N and TMR12_CH2 alternates.
29 PA8 bidirectional 5 V-tolerant general-purpose I/O (FT) with CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1 alternates.
30 PA9 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART1_TX (bootloader USART1 TX), I2C3_SMBA and TMR1_CH2 alternates.
31 PA10 bidirectional 5 V-tolerant general-purpose I/O (FT) with USART1_RX and TMR1_CH3 alternates; remap option I2S4_MCK.
32 PA11 bidirectional Standard-level (TC) I/O with USB_DM full-speed USB data line, plus USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4 alternates.
33 PA12 bidirectional Standard-level (TC) I/O with USB_DP full-speed USB data line, plus USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR alternates.
34 PA13 bidirectional 5 V-tolerant I/O (FT) with JTMS-SWDIO serial-wire debug data function.
35 VSS_2 power_in Digital ground for the I/O and logic.
36 VDD_2 power_in Digital supply for I/O pins and internal regulator, 2.6 to 3.6 V.
37 PA14 bidirectional 5 V-tolerant I/O (FT) with JTCK-SWCLK serial-wire debug clock function.
38 PA15 bidirectional 5 V-tolerant I/O (FT) with JTDI debug function; alternates SPI3_NSS and I2S3_WS, remap option SPI1_NSS / I2S1_WS / TMR2 channels.
39 PB3 bidirectional 5 V-tolerant I/O (FT) with JTDO debug function; alternates SPI3_SCK and I2S3_CK, remap option TRACESWO and SPI1_SCK.
40 PB4 bidirectional 5 V-tolerant I/O (FT) with NJTRST debug function; alternates SPI3_MISO and I2S3ext_SD, remap option I2C3_SDA and UART7_TX.
41 PB5 bidirectional 5 V-tolerant general-purpose I/O (FT) with SPI3_MOSI, I2S3_SD and I2C1_SMBA alternates; remap options SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2.
42 PB6 bidirectional 5 V-tolerant general-purpose I/O (FT) with I2C1_SCL, SPIM_IO3 and TMR4_CH1 alternates; remap option USART1_TX, I2S1_MCK and CAN2_TX.
43 PB7 bidirectional 5 V-tolerant general-purpose I/O (FT) with I2C1_SDA, XMC_NADV, SPIM_IO2 and TMR4_CH2 alternates; remap option USART1_RX and SPI4_SCK.
44 BOOT0 input Boot-mode select input; its weak pull-down (about 70 kΩ) cannot be disabled.
45 PB8 bidirectional 5 V-tolerant general-purpose I/O (FT) with SDIO1_D4, TMR4_CH3 and TMR10_CH1 alternates; remap option UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX.
46 PB9 bidirectional 5 V-tolerant general-purpose I/O (FT) with SDIO1_D5, TMR4_CH4 and TMR11_CH1 alternates; remap option UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX.
47 VSS_3 power_in Digital ground for the I/O and logic.
48 VDD_3 power_in Digital supply for I/O pins and internal regulator, 2.6 to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SD/MMC data-transfer clock frequency fPP 0 48 MHz CL ≤ 30 pF 77
Clock low time tW(CKL) 32 ns CL ≤ 30 pF 77
Clock high time tW(CKH) 30 ns CL ≤ 30 pF 77
Clock rise time tr 4 ns CL ≤ 30 pF 77
Clock fall time tf 5 ns CL ≤ 30 pF 77
CMD/D input setup time to CK tISU 2 ns CL ≤ 30 pF 77
CMD/D input hold time from CK tIH 0 ns CL ≤ 30 pF 77
CMD/D output valid time (MMC and SD high-speed mode) tOV 6 ns CL ≤ 30 pF 77
CMD/D output hold time (MMC and SD high-speed mode) tOH 0 ns CL ≤ 30 pF 77
CMD/D output valid default time (SD default mode) tOVD 7 ns CL ≤ 30 pF 77
CMD/D output hold default time (SD default mode) tOHD 0.5 ns CL ≤ 30 pF 77
USB transceiver startup time tSTARTUP 1 μs 78
USB operating voltage VDD 3 3.6 V 78
USB differential input sensitivity /USB_DP, USB_DM/ VDI 0.2 78
USB differential common-mode range VCM 0.8 2.5 V Includes VDI range 78
USB single-ended receiver threshold VSE 1.3 2 V 78
USB static output low level VOL 0.3 V 1.24 kΩ RL to 3.6 V 78
USB static output high level VOH 2.8 3.6 V 15 kΩ RL to VSS 78
USB_DP internal pull-up resistance RPU 0.97 1.24 1.58 kΩ VIN = VSS 78
USB full-speed rise time tr 4 20 ns CL ≤ 50 pF 78
USB full-speed fall time tf 4 20 ns CL ≤ 50 pF 78
USB rise/fall time matching (tr/tf) trfm 90 110 % 78
USB output signal crossover voltage VCRS 1.3 2 V 78
ADC supply voltage VDDA 2.6 3.6 V 79
ADC positive reference voltage VREF+ 2.6 V 79
Current into VDDA input pin IDDA 380 445 μA 79
Current into VREF input pin IVREF 200 220 μA 79
ADC clock frequency fADC 0.6 28 MHz 79
ADC sampling rate fS 0.05 2 MHz 79
External trigger frequency fTRIG 1.65 MHz fADC = 28 MHz 79
External trigger frequency fTRIG 17 1/fADC 79
Conversion voltage range VAIN 0 V VSSA or VREF- connected to ground 79
Injected trigger conversion latency tlat 107 ns fADC = 28 MHz 79
Injected trigger conversion latency tlat 3 1/fADC 79
Regular trigger conversion latency tlatr 71.4 μs fADC = 28 MHz 79
Regular trigger conversion latency tlatr 2 1/fADC 79
Sampling time tS 0.053 8.55 μs fADC = 28 MHz 79
Sampling time tS 1.5 239.5 1/fADC 79
Total conversion time (including sampling time) tCONV 0.5 9 μs fADC = 28 MHz 79
Total conversion time (including sampling time) tCONV 14 252 1/fADC 79

CAD (KiCad official)

  • Symbol: AT32F403ACGT7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: at32f403acgt7-etched.step / at32f403acgt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f403acgt7.step / at32f403acgt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (96 pp, sha256 602689c1ae94c051, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF