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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

AT32F402KBU7-4

ARTERY(雅特力) · IC · QFN-32-EP(4x4)

AT32F402KBU7-4 from ARTERY(雅特力), in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Digital power supply pin; VDD operating range is 2.4 V to 3.6 V and it powers the GPIOs, ERTC, LEXT, BPR and the LDO.
2	PF0	bidirectional	General-purpose I/O with standard TC level, multiplexed with TMR1_CH1 and I2C1_SDA, and used as the HEXT_IN high-speed crystal oscillator input.
3	PF1	bidirectional	General-purpose I/O with standard TC level, multiplexed with TMR1_CH2C, I2C1_SCL, SPI2_CS and I2S2_WS, and used as the HEXT_OUT crystal oscillator output.
4	NRST	bidirectional	Active-low device reset input and internal reset output with an internal weak pull-up (RPU 30 to 50 kΩ); VIL max is 0.8 V and VIH min is 2 V.
5	VDDA	power_in	Analog power supply for the ADC, which must be at the same potential as VDD (2.4 V to 3.6 V).
6	PA0	bidirectional	5 V-tolerant FTa I/O with analog function (5 V tolerant only in input modes; in analog mode the input must stay below VDD + 0.3 V), also ADC1_IN0, WKUP1 and TAMP2.
7	PA1	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN1, TMR2_CH2, I2C2_SDA and QSPI1_IO3.
8	PA2	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN2, TMR9_CH1, USART2_TX and QSPI1_CS.
9	PA3	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN3, TMR2_CH4, TMR9_CH2, I2S2_MCK and USART2_RX.
10	PA4	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN4, SPI1_CS, I2S1_WS, USART2_CK and TMR14_CH1.
11	PA5	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN5, SPI1_SCK, I2S1_CK, TMR2_CH1 and USART3_CK.
12	PA6	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN6, SPI1_MISO, I2S1_MCK, TMR3_CH1 and QSPI1_IO0.
13	PA7	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN7, SPI1_MOSI, I2S1_SD, TMR3_CH2 and QSPI1_IO1.
14	PB0	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN8, SPI1_MISO, TMR3_CH3, USART3_CK and QSPI1_IO0.
15	PB1	bidirectional	5 V-tolerant FTa I/O (input must stay below VDD + 0.3 V in analog mode), also ADC1_IN9, SPI1_MOSI, TMR3_CH4, USART3_RTS_DE and QSPI1_SCK.
16	PB2	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR2_CH4, TMR3_EXT, I2C3_SMBA, SPI3_MOSI, TMR14_CH1C and QSPI1_SCK.
17	VDD	power_in	Digital power supply pin; VDD operating range is 2.4 V to 3.6 V.
18	PA8	bidirectional	5 V-tolerant FT I/O, multiplexed with CLKOUT, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX and OTGFS1_SOF.
19	PA9	bidirectional	5 V-tolerant FT I/O, multiplexed with CLKOUT, TMR1_CH2, SPI2_SCK, I2S2_CK, USART1_TX, I2C1_SCL and OTGFS1_VBUS.
20	PA10	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR1_CH3, SPI2_MOSI, I2S2_SD, USART1_RX, I2C1_SDA and OTGFS1_ID.
21	PA11	bidirectional	5 V-tolerant FT I/O (leakage up to ±15 µA per Table 36), multiplexed with TMR1_CH4, I2C2_SCL, SPI2_CS, USART1_CTS, CAN1_RX and OTGFS1_D-.
22	PA12	bidirectional	5 V-tolerant FT I/O (leakage up to ±15 µA per Table 36), multiplexed with TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, CAN1_TX and OTGFS1_D+.
23	PA13	bidirectional	5 V-tolerant FT I/O that after reset is the SWDIO debug pin with its internal pull-up enabled, also multiplexed with IR_OUT, I2C1_SDA, SPI3_MISO and OTGFS1_OE.
24	PA14	bidirectional	5 V-tolerant FT I/O that after reset is the SWCLK debug pin with its internal pull-down enabled, also multiplexed with I2C1_SMBA, SPI3_MOSI, I2S3_SD and USART2_TX.
25	PA15	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR2_CH1, TMR2_EXT, SPI1_CS, I2S1_WS, SPI3_CS, USART1_TX, USART2_RX and QSPI1_IO2.
26	PB3	bidirectional	5 V-tolerant FTf I/O with 20 mA sink capability, multiplexed with SWO, TMR2_CH2, I2C2_SDA, SPI1_SCK, USART1_RX and QSPI1_IO3.
27	PB4	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR3_CH1, TMR11_BRK, I2C3_SDA, SPI1_MISO, USART1_CTS and QSPI1_SCK.
28	PB5	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR3_CH2, I2C3_SMBA, SPI1_MOSI, I2S1_SD, USART1_CK and QSPI1_IO0, and usable as wake-up input WKUP6.
29	PB6	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR4_CH1, TMR10_CH1C, I2C1_SCL, I2S1_MCK, USART1_TX and QSPI1_CS.
30	PB7	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR4_CH2, TMR11_CH1C, I2C1_SDA, USART1_RX and QSPI1_IO1.
31	PF11/BOOT0	bidirectional	5 V-tolerant FT pin that is sampled during reset as BOOT0 to select the boot mode; after reset it is PF11 in push-pull only and needs an external pull-down of 3.3 kΩ or less to ground.
32	PB8	bidirectional	5 V-tolerant FT I/O, multiplexed with TMR2_CH1, TMR2_EXT, TMR4_CH3, I2C1_SCL, USART1_TX and CAN1_RX.
33	EPAD (VSS / VSSA)	power_in	Exposed pad serving as the digital ground VSS and analog ground VSSA for the QFN32 package, with VSSA required to be at the same potential as VSS.

Key specifications

Parameter	Value
Manufacturer	ARTERY(雅特力)
Package	QFN-32-EP(4x4)
Category
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
外部主供电电压	VDDx-VSS	-0.3		4	V		37
不同供电引脚之间的电压差	/ΔVDDx/			50	mV		37
不同接地引脚之间的电压差	/VSSx-VSS/			50	mV		37
FTa引脚输入电压（设置为输入浮空、输入上拉或输入下拉）	VIN			6	V	FTa pin set to input floating, input pull-up or input pull-down; minimum printed as VSS-0.3	37
TC引脚输入电压	VIN			4	V	TC pin; minimum printed as VSS-0.3	37
经过VDD电源线的总电流（流入电流）	IVDD			150	mA	Total current through VDD power line (inflow)	37
经过VSS地线的总电流（流出电流）	IVSS			150	mA	Total current through VSS ground line (outflow)	37
任意GPIO和控制引脚上的输出灌电流	IIO			25	mA	Any GPIO and control pin, sink current	37
任意GPIO和控制引脚上的输出电流	IIO	-25			mA	Any GPIO and control pin, output current	37
储存温度范围	TSTG	-60		150	°C		37
最大结温度	TJ			125	°C		37
QSPI时钟频率	fSCK			108	MHz		61
数据输入建立时间	ts(IN)	2			ns		61
数据输入保持时间	th(IN)	4.5			ns		61
数据输出有效时间	tv(OUT)		1.5	3	ns		61
数据输出保持时间	th(OUT)	0			ns		61
OTGFS收发器启动时间	tSTARTUP			1	μs		63
OTGFS操作电压	VDD	3		3.6	V		63
差分输入灵敏度 I（OTGFS_D+/D-）	VDI	0.2					63
差分共模范围	VCM	0.8		2.5	V	Includes VDI range	63
单端接收器阈值	VSE	1.3		2			63
静态输出低电平	VOL			0.3	V	1.24 kΩ RL to 3.6 V	63
静态输出高电平	VOH	2.8		3.6	V	15 kΩ RL to VSS	63
OTGFS_D+内部上拉电阻	RPU	0.97	1.24	1.58	kΩ	Idle state, VIN = VSS	63
OTGFS_D+内部上拉电阻	RPU	1.66	2.26	3.09	kΩ	Receive state, VIN = VSS	63
OTGFS_D+/D-内部下拉电阻	RPD	15	19	25	kΩ	VIN = VDD	63
上升时间	tr	4		20	ns	CL ≤ 50 pF	63
下降时间	tf	4		20	ns	CL ≤ 50 pF	63
上升下降时间匹配 tr/tf	trfm	90		110	%		63
输出信号交叉电压	VCRS	1.3		2	V		63
ADC供电电压	VDDA	2.4		3.6	V		64
在VDDA输入脚上的电流	IDDA		475	560	μA		64
ADC时钟频率	fADC	0.6		28	MHz		64
采样速率	fS	0.05		2	MHz		64
外部触发频率	fTRIG			1.65	MHz	fADC = 28 MHz	64
外部触发频率	fTRIG			17	1/fADC		64
转换电压范围	VAIN	0			V	VREF- internally connected to ground; maximum printed as VREF+	64
内部采样和保持电容	CADC		8.5	13	pF		64
触发转换时延	tlatr			71.4	ns	fADC = 28 MHz	64
触发转换时延	tlatr			2	1/fADC		64
采样时间	tS	0.053		8.55	μs	fADC = 28 MHz	64
采样时间	tS	1.5		239.5	1/fADC		64
总转换时间（包括采样时间）	tCONV	0.5		9	μs	fADC = 28 MHz	64
总转换时间（包括采样时间）	tCONV	14		252	1/fADC		64
最大外部输入阻抗，TS=1.5周期	RAIN			0.35	kΩ	fADC = 14 MHz; TS = 1.5 cycles; tS = 0.11 μs	64
最大外部输入阻抗，TS=7.5周期	RAIN			3.9	kΩ	fADC = 14 MHz; TS = 7.5 cycles; tS = 0.54 μs	64
最大外部输入阻抗，TS=13.5周期	RAIN			7.4	kΩ	fADC = 14 MHz; TS = 13.5 cycles; tS = 0.96 μs	64
最大外部输入阻抗，TS=28.5周期	RAIN			16.3	kΩ	fADC = 14 MHz; TS = 28.5 cycles; tS = 2.04 μs	64
最大外部输入阻抗，TS=41.5周期	RAIN			24	kΩ	fADC = 14 MHz; TS = 41.5 cycles; tS = 2.96 μs	64
最大外部输入阻抗，TS=55.5周期	RAIN			32.3	kΩ	fADC = 14 MHz; TS = 55.5 cycles; tS = 3.96 μs	64
最大外部输入阻抗，TS=71.5周期	RAIN			41.8	kΩ	fADC = 14 MHz; TS = 71.5 cycles; tS = 5.11 μs	64
最大外部输入阻抗，TS=239.5周期	RAIN			50	kΩ	fADC = 14 MHz; TS = 239.5 cycles; tS = 17.11 μs	64

CAD (KiCad official)

Symbol: AT32F402KBU7-4
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: at32f402kbu7-4-etched.step / at32f402kbu7-4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f402kbu7-4.step / at32f402kbu7-4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY(雅特力) datasheet (82 pp, sha256 60bf116b09ab059e, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF