AT25XE161D-MAHN-T from Adesto Technologies, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS	input	Chip select input: asserting CS low selects the device and starts an operation, and deasserting it deselects the device, places SO in high-impedance, and returns it to standby (not Deep Power-Down).
2	SO (I/O1)	bidirectional	Serial output that shifts data out on the falling edge of SCK and is high-impedance when the device is deselected; it acts as I/O1 in dual and quad read modes.
3	WP (I/O2)	bidirectional	Write protect input that controls hardware locking of the Status Register, internally pulled high and recommended to be tied to VCC, and that becomes I/O2 when the QE bit is set.
4	GND	power_in	Ground reference for the power supply, to be connected to system ground.
5	SI (I/O0)	bidirectional	Serial input latched on the rising edge of SCK for all command, address and write data, and becomes I/O0 in multi-I/O read modes.
6	SCK	input	Serial clock: command, address and input data on SI are latched on the rising edge, and output data on SO is clocked out on the falling edge.
7	HOLD/RESET (I/O3)	bidirectional	Internally pulled-high pin configurable as an active-low HOLD that pauses serial communication or as an active-low RESET per Status Register 3 bit 7 when QE is cleared, and it is I/O3 when QE is set.
8	VCC	power_in	Device power supply pin for 1.65V to 3.6V operation; invalid VCC voltages may produce spurious results and should not be attempted.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Adesto Technologies
Package	USON-8-EP(2x3)
Category	Memory
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Temperature under bias		-55		125	°C		125
Storage Temperature		-65		150	°C		125
All input voltages (including NC pins) with respect to ground		-0.6			V	upper limit printed as VCC + 0.5V	125
All output voltages with respect to ground		-0.6			V	upper limit printed as VCC + 0.5V	125
Operating Temperature (Case)		-40		85	°C		125
VCC Power Supply	VCC	1.65		3.6	V		125
Ultra-Deep Power-Down Current	IUDPD		7	250	nA	CS = VCC. All other inputs at 0V or VCC	125
Deep Power-Down Current	IDPD		8.2	17.5	µA	CS, RESET, WP = VCC. All other inputs at 0V or VCC	125
Standby Current	ISB		30	50	µA	CS, RESET, WP = VCC. All other inputs at 0V or VCC	125
Active Current, SPI (33 MHz)	ICC1		5.2	8.5	mA	SPI (33 MHz) IOUT = 0mA	125
Active Current, SPI (108 MHz)	ICC1		8	12.5	mA	SPI (108 MHz) IOUT = 0mA	125
Active Current, Dual (108 MHz)	ICC1		10.2	15	mA	Dual (108 MHz) IOUT = 0mA	125
Active Current, Quad (108 MHz)	ICC1		12.4	17.5	mA	Quad (108 MHz) IOUT = 0mA	125
Active Current, Program Operation	ICC3		8.6	13	mA	CS = VCC	125
Active Current, Erase Operation	ICC4		9.6	14.5	mA	CS = VCC	125
Input Load Current	ILI	-2		2	µA	All inputs at CMOS levels	125
Output Leakage Current	ILO	-2		2	µA	All inputs at CMOS levels	126
Output Low Voltage	VOL			0.2	V	IOL = 100 µA	126
Maximum clock frequency for all operations (except 03h, 0Bh, 3Bh)	fSCK			108	MHz	1.65V to 3.6V column	126
Maximum clock frequency for 0Bh and 3Bh commands	fSCK			104	MHz	1.65V to 3.6V column	126
Maximum clock frequency for 03h command (Read Array, Low Frequency)	fRDLF			40	MHz		126
SCK High Time	tCLKH	4.5			ns		126
SCK Low Time	tCLKL	4.5			ns		126
Minimum CS High Time	tCSH	35			ns		126
CS Low Setup Time (relative to clock)	tCSLS	6			ns		126
CS Low Hold Time (relative to clock)	tCSLH	6			ns		126
Data In Setup Time	tDS	2			ns		127
Data In Hold Time	tDH	1			ns		127
Output Disable Time	tDIS			8	ns		127
Output Valid Time	tV			8	ns		127
Output Hold Time	tOH	0			ns		127
HOLD Low to Output High-Z	tHLQZ			7	ns		127
HOLD High to Output Low-Z	tHHQX			7	ns		127
Write Protect Setup Time	tWPS	20			ns		127
Write Protect Hold Time	tWPH	100			ns		127
CS High to Deep Power-Down	tEDPD			3	µs		127
CS High to Ultra Deep Power-Down	tEUDPD			3	µs		127
Resume from Terminate Command Time	tSWTERM			50	µs		127
Resume from Software Reset Time	tSWRST			260	µs		127
Resume from Ultra Deep Power-Down Time	tRUDPD		160	260	µs	maximum valid for UDPD hold time >400ms	127
Resume from Deep Power-Down Time	tRDPD			35	µs		127
Read-Modify-Write Time	tRWM		13	82	ms	1.65V - 3.6V column	128
Page Program Time (256 Bytes)	tPP		4.4	6.5	ms	1.65V - 3.6V column	128
Page Erase Time	tPE		10	75	ms	1.65V - 3.6V column	128
Block Erase Time 4 kB	tBLKE		85	180	ms	1.65V - 3.6V column	128
Block Erase Time 32 kB	tBLKE		590	1300	ms	1.65V - 3.6V column	128
Block Erase Time 64 kB	tBLKE		1200	2500	ms	1.65V - 3.6V column	128
Resume Time (Program)	tRES		8	10	µs	1.65V - 3.6V column	128
Resume Time (Erase)	tRES		8	10	µs	1.65V - 3.6V column	128
OTP Security Register Program Time (<= 10K)	tOTPP		5	6	ms	1.65V - 3.6V column	128
Write Status Register Time	tWRSR		7.5	15	ms	1.65V - 3.6V column	128
Minimum VCC to full operation permitted	tVCSL			260	µs		129
VCC rise time (from 0V to VCCmin)	tVR	1		30000	µs/V		129
VCC brown-out low time	tPWD	300			µs		129
Maximum VCC brown-out	VPWDMAX			0.2	V		129
Program Time (Byte Program)	tBP		32		µs	program time after first byte varies	128
Chip Erase Time (16M density)	tCHPE		37		sec	1.65V - 3.6V column	128
Suspend Time (Program)	tSUS		50		µs	1.65V - 3.6V column	128

CAD (KiCad official)

Symbol: AT25XE161D-MAHN-T
Footprint: Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm
3D model: USON-8-EP(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: at25xe161d-mahn-t-etched.step / at25xe161d-mahn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25xe161d-mahn-t.step / at25xe161d-mahn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Adesto Technologies datasheet (141 pp, sha256 33fdbf34249e1966, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AT25XE161D-MAHN-T

Verified AT25XE161D-MAHN-T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README