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AT25XE021A-SSHN-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25XE021A-SSHN-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25XE021A-SSHN-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select: asserting CS low selects the device and a high-to-low transition starts an operation, while deasserting it places the device in standby (not Deep Power-Down) with SO high-impedance and SI ignored.
2 SO (I/O1) bidirectional Serial output shifts data out on the falling edge of SCK and is high-impedance whenever CS is deasserted; in Dual-Output Read it functions as I/O1.
3 WP input Write protect controls the hardware locking of protected sectors; it is internally pulled high and may be left floating, but connecting it to VCC is recommended.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SI (I/O0) bidirectional Serial input latches command, address and input data on the rising edge of SCK and is ignored while the device is deselected; in Dual-Output Read it functions as I/O0.
6 SCK input Serial clock controls data flow: SI data is latched on the rising edge of SCK and SO data is clocked out on the falling edge.
7 HOLD input Asserting HOLD low (with CS asserted and SCK low) pauses serial communication without deselecting or resetting the device, with SCK and SI ignored and SO high-impedance; it is internally pulled high and may be left floating if unused.
8 VCC power_in Device power supply within 1.65V to 3.6V; operation at invalid VCC voltages may produce spurious results and should not be attempted.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.2 0.6 µA CS = VCC. All other inputs at 0V or VCC 38
Deep Power-Down Current IDPD 4.5 15 µA CS = VCC. All other inputs at 0V or VCC 38
Standby Current ISB 25 40 µA CS = VCC. All other inputs at 0V or VCC 38
Active Current, Low Power Read (03h, 0Bh) ICC1 3 4.5 mA f = 1MHz; IOUT = 0mA 38
Active Current, Low Power Read (03h, 0Bh) ICC1 3.5 5.25 mA f = 20MHz; IOUT = 0mA 38
Active Current, Read Operation ICC2 3.5 5.25 mA f = 50MHz; IOUT = 0mA 38
Active Current, Program Operation ICC3 9 10.5 mA CS = VCC 38
Active Current, Erase Operation ICC4 8 11 mA CS = VCC 38
Input Load Current ILI 1 µA All inputs at CMOS levels 38
Output Leakage Current ILO 1 µA All inputs at CMOS levels 38
Output Low Voltage VOL 0.2 0.4 V IOL = 100µA 38
Maximum Clock Frequency for All Operations (including 0Bh opcode) fCLK 70 MHz 39
Maximum Clock Frequency for 03h Opcode (Read Array, Low Frequency) fRDLF 25 MHz 39
Maximum Clock Frequency for 3B Opcode fRDDO 40 MHz 39
Clock High Time tCLKH 4.5 ns 39
Clock Low Time tCLKL 4 ns 39
Chip Select High Time tCSH 35 ns 39
Chip Select Low Setup Time (relative to Clock) tCSLS 6 ns 39
Chip Select Low Hold Time (relative to Clock) tCSLH 6 ns 39
Chip Select High Setup Time (relative to Clock) tCSHS 6 ns 39
Chip Select High Hold Time (relative to Clock) tCSHH 6 ns 39
Data In Setup Time tDS 2 ns 39
Data In Hold Time tDH 1 ns 39
Output Disable Time tDIS 8 ns 39
Output Valid Time tV 7.5 ns 39
HOLD Low Setup Time (relative to Clock) tHLS 6 ns 39
HOLD Low Hold Time (relative to Clock) tHLH 6 ns 39
HOLD High Setup Time (relative to Clock) tHHS 6 ns 39
HOLD High Hold Time (relative to Clock) tHHH 6 ns 39
HOLD Low to Output High-Z tHLQZ 7 ns 39
HOLD High to Output Low-Z tHHQX 7 ns 39
Write Protect Setup Time tWPS 20 ns 39
Write Protect Hold Time tWPH 100 ns 39
Chip Select High to Deep Power-Down tEDPD 3 µs 39
Chip Select High to Ultra Deep Power-Down tEUDPD 3 µs 40
Software Reset Time tSWRST 60 µs 40
Exit Ultra Deep Power-Down Time tXUDPD 70 µs 40
Chip Select High to Standby Mode tRDPD 8 µs 40
Page Program Time (256 Bytes) tPP 2 5 ms 40
Page Erase Time (256 Bytes) tPE 6 20 ms 40
Block Erase Time (4 Kbytes) tBLKE 45 100 ms 40
Block Erase Time (32 Kbytes) tBLKE 360 600 ms 40
Block Erase Time (64 Kbytes) tBLKE 720 1200 ms 40
Chip Erase Time tCHPE 2.4 4.8 s 40
OTP Security Register Program Time tOTPP 400 950 µs 40
VCC for device initialization VPWD 1 V 41
Minimum duration for device initialization tPWD 300 µs 41
Minimum VCC to chip select low time for Read command tVCSL 70 µs 41
VCC rise time tVR 1 500000 µs/V 41
Power on reset voltage VPOR 1.45 1.6 V 41
Power up delay time before Program or Erase is allowed tPUW 3 ms 41
Temperature under Bias -55 125 °C 37
Storage Temperature -65 150 °C 37
Absolute Maximum VCC VCC 3.96 V 37
All Output Voltages with Respect to Ground -0.6 4.2 V Max VCC of 3.6V + 0.6V 37
All Input Voltages with Respect to Ground -0.6 4.2 V excluding VCC pin, including NC pins; Max VCC of 3.6V + 0.6V 37
Operating Temperature (Case) Ind. -40 85 °C Industrial 37
VCC Power Supply VCC 1.65 3.6 V 37

CAD (KiCad official)

  • Symbol: AT25XE021A-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25xe021a-sshn-t-etched.step / at25xe021a-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25xe021a-sshn-t.step / at25xe021a-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (51 pp, sha256 aaaa9900b0cd358d, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF