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AT25XE011-SSHN-T

Public Made by Adom

by adom

Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25XE011-SSHN-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25XE011-SSHN-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select: asserting selects the device, deasserting deselects it into standby (not Deep Power-Down) with SO high-impedance, and a high-to-low transition is required to start an operation.
2 SO (I/O1) bidirectional Serial output that shifts data out on the falling edge of SCK, acts as I/O1 in Dual-Output Read, and is high-impedance when the device is deselected.
3 WP input Active-low write protect controlling hardware locking of protected sectors; internally pulled high, may be left floating if unused, but connecting to VCC is recommended.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SI (I/O0) bidirectional Serial input that shifts in commands, addresses and data latched on the rising edge of SCK, becomes output I/O0 in Dual-Output Read, and is ignored when the device is deselected.
6 SCK input Serial clock controlling data flow, with input latched on the rising edge and output clocked out on the falling edge of SCK.
7 HOLD input Active-low hold that pauses serial communication without deselecting the device (CS asserted and SCK low required to start a Hold); internally pulled high, may be left floating, connecting to VCC recommended.
8 VCC power_in Device power supply (1.65V to 3.6V operating range); operation at invalid VCC voltages may produce spurious results.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under bias -55 125 °C 28
Storage temperature -65 150 °C 28
Absolute maximum VCC VCC 3.96 V 28
Output voltages with respect to ground -0.6 4.2 V Max VCC of 3.6V + 0.6V 28
Input voltages with respect to ground -0.6 4.2 V excluding VCC pin, including NC pins; Max VCC of 3.6V + 0.6V 28
VCC power supply VCC 1.65 3.6 V 28
Operating temperature (case) -40 85 °C Ind. 28
Ultra-Deep Power-Down current IUDPD 0.2 0.6 µA CS = VCC. All other inputs at 0V or VCC 29
Deep Power-Down current IDPD 4.5 15 µA CS = VCC. All other inputs at 0V or VCC 29
Standby current ISB 25 40 µA CS = VCC. All other inputs at 0V or VCC 29
Active current, low power read (03h, 0Bh) ICC1 3.5 7 mA f = 1MHz; IOUT = 0mA 29
Active current, read operation ICC2 4 7 mA f = 50MHz; IOUT = 0mA 29
Active current, program operation ICC3 10 13 mA CS = VCC 29
Active current, erase operation ICC4 9 13 mA CS = VCC 29
Input load current ILI 1 µA All inputs at CMOS levels 29
Output leakage current ILO 1 µA All inputs at CMOS levels 29
Output low voltage VOL 0.2 V IOL = 100µA 29
Maximum clock frequency for all operations (including 0Bh opcode) fCLK 104 MHz 30
Maximum clock frequency for 03h opcode (Read Array, Low Frequency) fRDLF 25 MHz 30
Maximum clock frequency for 3B opcode fRDDO 50 MHz 30
Clock high time tCLKH 4 ns 30
Clock low time tCLKL 4 ns 30
Chip select high time tCSH 35 ns 30
Chip select low setup time (relative to clock) tCSLS 6 ns 30
Chip select low hold time (relative to clock) tCSLH 6 ns 30
Chip select high setup time (relative to clock) tCSHS 6 ns 30
Data in setup time tDS 2 ns 30
Data in hold time tDH 1 ns 30
Output disable time tDIS 8 ns 30
Output valid time tV 8 ns 30
Output hold time tOH 0 ns 30
HOLD low setup time (relative to clock) tHLS 6 ns 30
HOLD high setup time (relative to clock) tHHS 6 ns 30
HOLD low to output High-Z tHLQZ 7 ns 30
HOLD high to output Low-Z tHHQX 7 ns 30
Write protect setup time tWPS 20 ns 30
Write protect hold time tWPH 100 ns 30
Chip select high to Deep Power-Down tEDPD 2 µs 30
Chip select high to Ultra Deep Power-Down tEUDPD 3 µs 31
Software reset time tSWRST 60 µs 31
Minimum chip select low to exit Ultra Deep Power-Down tCSLU 20 ns 31
Exit Ultra Deep Power-Down time tXUDPD 70 µs 31
Chip select high to standby mode tRDPD 8 µs 31
Page program time tPP 2 3 ms 256 Bytes 31
Page erase time tPE 7 25 ms 256 Bytes 31
Block erase time tBLKE 50 75 ms 4 Kbytes 31
Block erase time tBLKE 400 500 ms 32 Kbytes 31
Chip erase time tCHPE 1600 2200 ms 31
Write status register time tWRSR 20 40 ms 31
VCC for device initialization VPWD 1 V 32
Minimum duration for device initialization tPWD 300 µs 32
Minimum VCC to chip select low time for Read command tVCSL 70 µs 32
VCC rise time tVR 1 500000 µs/V 32
Power on reset voltage VPOR 1.45 1.6 V 32
Power up delay time before Program or Erase is allowed tPUW 3 ms 32

CAD (KiCad official)

  • Symbol: AT25XE011-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25xe011-sshn-t-etched.step / at25xe011-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25xe011-sshn-t.step / at25xe011-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (41 pp, sha256 d7dfb18a10d10fa3, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF