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AT25SL321-MBUE-T

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Adesto Technologies NOR FLASH, USON-8(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat25sl321-mbue-tfactory-2.0.0extractor-text

Verified AT25SL321-MBUE-T

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 9 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT25SL321-MBUE-T · USON-8(3x4) · 9 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 9 pin names found in the 78-page datasheet
  • ✓distributor: lcsc C2062099, digikey 1265-1281-2-ND, mouser 988-AT25SL321-MBUE-T
  • ✓family: Winbond_USON-8-2EP_3x4mm_P0.8mm_EP0.2x0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1jua54d_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.73)
  • ✓pads: 9 pins = 9 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 9 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at25sl321-mbue-t.kicad_sym✓ at25sl321-mbue-t.kicad_mod✓ at25sl321-mbue-t.step
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Ray Publish 0.1.0 ff2ed42 4d ago

AT25SL321-MBUE-T

Adesto Technologies · NOR FLASH · USON-8(3x4)

AT25SL321-MBUE-T from Adesto Technologies, in a USON-8(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select: high deselects the device and tri-states the outputs (standby), low enables it, and a falling edge is required before any instruction after power-up.
2 SO (IO1) bidirectional Serial data output clocked out on the falling edge of SCK, high-impedance when deselected, and bidirectional IO1 in Dual and Quad modes.
3 WP (IO2) bidirectional Active-low write protect for the Status Register, which becomes IO2 in Quad I/O and QPI operation when the QE bit is set.
4 GND power_in Ground reference for the VCC supply, to be connected to system ground.
5 SI (IO0) bidirectional Serial data input latched on the rising edge of SCK for commands, addresses and data, and bidirectional IO0 in Dual and Quad modes.
6 SCK input Serial clock input that times the interface, with inputs latched on the rising edge and data shifted out on the falling edge, up to 104 MHz.
7 HOLD (IO3) bidirectional Active-low hold that pauses a serial sequence without resetting it, which becomes IO3 in Quad I/O and QPI operation.
8 VCC power_in Single device power supply for read, program and erase, operating range 1.7 V to 2.0 V.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package USON-8(3x4)
Category Memory
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 1.7 2 V FR = 104MHz (Single/Dual/Quad SPI); fR = 50MHz (Read Data 03h) 62
Ambient Operating Temperature TA -40 85 ˚C Industrial 62
Supply Voltage (absolute max) VCC -0.6 V Upper limit printed as VCC+0.4 62
Voltage Applied to Any Pin VIO -0.6 V Relative to Ground; upper limit printed as VCC +0.4 62
Transient Voltage on any Pin VIOT -1 V <20nS Transient, Relative to Ground; upper limit printed as VCC +1.0V 62
Storage Temperature TSTG -65 150 ˚C 62
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model 62
Erase/Program Cycles 100000 Cycles 4KB Block, 32/64KB block or full chip. 62
Data Retention 20 years Full Temperature Range 62
VCC(min) to CS Low tVSL 10 µs 63
Time Delay Before Write Instruction tPUW 1 10 ms 63
Write Inhibit Threshold Voltage VWI 1 1.4 V 63
WP pin High Voltage VHH 8.5 9.5 V 64
Input Capacitance CIN 6 pF VIN=0V 64
Output Capacitance COUT 8 pF VOUT=0V 64
Input Leakage ILI -2 2 µA 64
I/O Leakage ILO -2 2 µA 64
Standby Current ICC1 10 50 µA CS=VCC, VIN=GND or VCC 64
Power Down Current ICC2 2 20 µA CS=VCC, VIN=GND or VCC 64
Current Read Data/Dual/Quad 1MHz ICC3 7 mA C=0.1 VCC / 0.9VCC 64
Current Read Data/Dual/Quad 50MHz ICC3 15 mA C=0.1 VCC / 0.9VCC 65
Current Read Data/Dual/Quad 80MHz ICC3 18 mA C=0.1 VCC / 0.9VCC 65
Current Read Data/Dual/Quad 104MHz ICC3 20 mA C=0.1 VCC / 0.9VCC 65
Current Write Status Register ICC4 10 20 mA CS=VCC 65
Current Page Program ICC5 15 25 mA CS=VCC 65
Current Block Erase ICC6 15 25 mA CS=VCC 65
Current Chip Erase ICC7 15 25 mA CS=VCC 65
Input Low Voltages VIL -0.5 V Max printed as VCC x0.2 65
Output Low Voltages VOL 0.2 V IOL= 100µA 65
Clock frequency, all instructions except Read Data (03h) FR 0 104 MHz 66
Clock freq. Read Data instruction (03h) fR 0 50 MHz 66
Clock High, Low Time except Read Data (03h) tCLH, tCLL 4.5 ns 66
Clock High, Low Time for Read Data (03h) tCRLH, tCRLL 8 ns 66
CS Active Setup Time relative to Clock tSLCH 5 ns 66
CS Not Active Hold Time relative to Clock tCHSL 5 ns 66
Data In Setup Time tDVCH 2 ns 66
Data In Hold Time tCHDX 5 ns 66
CS Active Hold Time relative to Clock tCHSH 5 ns 66
CS Not Active Setup Time relative to Clock tSHCH 5 ns 66
CS Deselect Time tSHSL 100 ns for Read instructions/ Write, Erase and Program instructions 66
Output Disable Time tSHQZ 7 ns 66
Clock Low to Output Valid tCLQV (tV1) 7 ns 66
Clock Low to Output Valid (Except Main Read) tCLQV (tV2) 8 ns 66
Output Hold Time tCLQX 1.5 ns 67
HOLD to Output Low-Z tHHQX 7 ns 67
HOLD to Output High-Z tHLQZ 12 ns 67
CS High to Power Down Mode tDP 3 µs 67
CS High to Standby Mode without Electronic Signature Read tRES1 3 µs 67
CS High to Standby Mode with Electronic Signature Read tRES2 1.8 µs 67
CS High to next Instruction after Suspend tSUS 30 µs 67
CS High to next Instruction after Reset tRST 30 µs 67
Write Status Register Time tw 10 15 ms 67
Byte Program Time tBP 10 150 µs 67
Page Program Time tPP 0.6 5 ms 67
Page Program Time (ACC = 9V) tEP 0.3 3 ms 67
Block Erase Time (4KB) tSE 0.06 0.4 s 67
Block Erase Time (32KB) tBE1 0.2 1.5 s 67
Block Erase Time (64KB) tBE2 0.35 2 s 67
Chip Erase Time tCE 20 80 s 67

CAD (KiCad official)

  • Symbol: AT25SL321-MBUE-T
  • Footprint: Package_SON:Winbond_USON-8-2EP_3x4mm_P0.8mm_EP0.2x0.8mm
  • 3D model: USON-8(3x4), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.55 mm nominal UFQFPN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: at25sl321-mbue-t-etched.step / at25sl321-mbue-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sl321-mbue-t.step / at25sl321-mbue-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (78 pp, sha256 d7fbe26594e5acee, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF