component
AT25SF641B-SHB-T
Public Made by Adomby adom
Adesto Technologies NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
AT25SF641B-SHB-T
Adesto Technologies · NOR FLASH · SOIC-8-208mil
AT25SF641B-SHB-T from Adesto Technologies, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Active-low chip select: asserting it selects the device, a high-to-low transition starts an operation and a low-to-high transition ends it, and deasserting it places the device in standby after any self-timed operation completes. |
| 2 | SO (I/O1) | bidirectional | Serial output that clocks data out on the falling edge of SCK, acts as I/O1 in Dual and Quad modes, and is high-impedance when the device is deselected. |
| 3 | WP (I/O2) | bidirectional | Write protect that controls hardware locking of the status register, becomes I/O2 in Quad modes, and is internally pulled high so it can float if unused (connecting it to VCC is recommended). |
| 4 | GND | power_in | Ground reference for the power supply, to be connected to system ground. |
| 5 | SI (I/O0) | bidirectional | Serial input that latches command, address and data on the rising edge of SCK, and becomes I/O0 for Dual and Quad commands. |
| 6 | SCK | input | Serial clock: command, address and input data are latched on the rising edge of SCK and output data is clocked out on the falling edge. |
| 7 | HOLD (I/O3) | bidirectional | Hold pin that pauses serial communication without deselecting the device (CS asserted and SCK low required), becomes I/O3 in Quad modes, and is internally pulled high so it can float if unused (connecting it to VCC is recommended). |
| 8 | VCC | power_in | Device power supply pin, operating range 2.7 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Adesto Technologies |
| Package | SOIC-8-208mil |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature (Case), Industrial | -40 | 85 | °C | Industrial | 47 | ||
| VCC Power Supply | VCC | 2.7 | 3.6 | V | 47 | ||
| Temperature under Bias | -55 | 125 | °C | 47 | |||
| Storage Temperature | -65 | 150 | °C | 47 | |||
| All Input Voltages (including NC Pins) with Respect to Ground | -0.5 | 4 | V | 47 | |||
| Deep Power-Down Current | IDPD | 2 | 5 | µA | CS, HOLD, WP = VIH; all inputs at CMOS levels | 47 | |
| Standby Current | ISB | 13 | 25 | µA | CS, HOLD, WP = VIH; all inputs at CMOS levels | 47 | |
| Active Current, Read (03h, 0Bh) Operation | ICC1 | 3 | 4.5 | mA | f = 20 MHz; IOUT = 0 | 47 | |
| Active Current, Read (03h, 0Bh) Operation | ICC1 | 4 | 5.5 | mA | f = 50 MHz; IOUT = 0 | 47 | |
| Active Current, Read (03h, 0Bh) Operation | ICC1 | 5 | 7 | mA | f = 85 MHz; IOUT = 0 | 47 | |
| Active Current, Read (3Bh, BBh) Operation (Dual) | ICC2 | 5 | 7 | mA | f = 50 MHz; IOUT = 0 | 47 | |
| Active Current, Read (3Bh, BBh) Operation (Dual) | ICC2 | 7 | 9.5 | mA | f = 85 MHz and 104 MHz; IOUT = 0 | 47 | |
| Active Current, Read (6Bh, EBh) Operation (Quad) | ICC3 | 6 | 8.5 | mA | f = 50 MHz; IOUT = 0 | 47 | |
| Active Current, Read (6Bh, EBh) Operation (Quad) | ICC3 | 9 | 12.5 | mA | f = 85 MHz and 104 MHz; IOUT = 0 | 47 | |
| Active Current, Program Operation | ICC4 | 17 | mA | CS = VCC | 47 | ||
| Active Current, Write to Non-Volatile Status Register | ICC5 | 12 | mA | CS = VCC | 48 | ||
| Active Current, Erase Operation | ICC6 | 15 | mA | CS = VCC | 48 | ||
| Input Load Current | ILI | -2 | 2 | µA | All inputs at CMOS levels | 48 | |
| Output Leakage Current | ILO | -2 | 2 | µA | All inputs at CMOS levels | 48 | |
| Output Low Voltage | VOL | 0.4 | V | IOL = 100 µA | 48 | ||
| Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, and 6Bh | fCLK | 104 | MHz | 48 | |||
| Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh | fCLK1 | 85 | MHz | 48 | |||
| Maximum Clock Frequency for 03h opcode | fCLK2 | 55 | MHz | 48 | |||
| Clock High Time | tCLKH | 4 | ns | 49 | |||
| Clock Low Time | tCLKL | 4 | ns | 49 | |||
| Clock Rise Time, Peak-to-Peak (Slew Rate) | tCLKR | 0.1 | V/ns | Not 100% tested (guaranteed by design and characterization) | 49 | ||
| Clock Fall Time, Peak-to-Peak (Slew Rate) | tCLKF | 0.1 | V/ns | Not 100% tested (guaranteed by design and characterization) | 49 | ||
| CS High Time | tCSH | 20 | ns | 49 | |||
| CS Low Setup Time (relative to Clock) | tCSLS | 5 | ns | 49 | |||
| CS Low Hold Time (relative to Clock) | tCSLH | 5 | ns | 49 | |||
| CS High Setup Time (relative to Clock) | tCSHS | 5 | ns | 49 | |||
| CS High Hold Time (relative to Clock) | tCSHH | 5 | ns | 49 | |||
| Data In Setup Time | tDS | 2 | ns | 49 | |||
| Data In Hold Time | tDH | 2 | ns | 49 | |||
| Output Disable Time | tDIS | 6 | ns | Not 100% tested (guaranteed by design and characterization) | 49 | ||
| Output Valid Time | tV | 7 | ns | 49 | |||
| Output Hold Time | tOH | 0 | ns | 49 | |||
| HOLD Low Setup Time (relative to Clock) | tHLS | 5 | ns | 49 | |||
| HOLD Low Hold Time (relative to Clock) | tHLH | 5 | ns | 49 | |||
| HOLD High Setup Time (relative to Clock) | tHHS | 5 | ns | 49 | |||
| HOLD High Hold Time (relative to Clock) | tHHH | 5 | ns | 49 | |||
| HOLD Low to Output High-Z | tHLQZ | 6 | ns | Not 100% tested (guaranteed by design and characterization) | 49 | ||
| HOLD High to Output High-Z | tHHQZ | 6 | ns | Not 100% tested (guaranteed by design and characterization) | 49 | ||
| CS High to Standby Mode Without Electronic Signature Read | tRES1 | 20 | µs | 49 | |||
| CS High to Standby Mode With Electronic Signature Read | tRES2 | 20 | µs | 49 | |||
| CS High to Next Instruction After Suspend | tSUS | 20 | µs | 49 | |||
| Write Protect Setup Time | tWPS | 20 | ns | 49 | |||
| Write Protect Hold Time | tWPH | 100 | ns | 49 | |||
| CS High to Deep Power-Down | tEDPD | 20 | µs | 49 | |||
| CS High to Standby Mode | tRDPD | 20 | µs | 49 | |||
| Resume Deep Power-Down, CS High to ID | tRDPO | 20 | µs | 49 | |||
| Page Program Time (256 Bytes) | tPP | 0.6 | 3 | ms | 50 | ||
| First Byte Program Time | tBP1 | 30 | 50 | µs | 50 | ||
| Second Byte Program Time | tBP2 | 2.5 | 12 | µs | 50 | ||
| Block Erase Time 4 kbytes | tBLKE | 60 | 150 | ms | 50 | ||
| Block Erase Time 32 kbytes | tBLKE | 120 | 350 | ms | 50 | ||
| Block Erase Time 64 kbytes | tBLKE | 200 | 560 | ms | 50 | ||
| Chip Erase Time | tCHPE | 30 | 60 | sec | 50 | ||
| Write Status Register Time | tWRSR | 5 | 30 | ms | 50 | ||
| Minimum VCC to CS Low Time | tVCSL | 70 | µs | 50 |
CAD (KiCad official)
- Symbol:
AT25SF641B-SHB-T - Footprint:
Package_SO:SOIC-8_5.3x5.3mm_P1.27mm - 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
- 3D model files:
at25sf641b-shb-t-etched.step/at25sf641b-shb-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at25sf641b-shb-t.step/at25sf641b-shb-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Adesto Technologies datasheet (58 pp, sha256
22ce2d0cb9caf7ae, retrieved 2026-11-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).