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AT25SF641B-MHB-T

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Dialog Semiconductor/Adesto Adesto Technologies NOR FLASH, UDFN-8(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AT25SF641B-MHB-T

Dialog Semiconductor/Adesto Adesto Technologies · NOR FLASH · UDFN-8(5x6)

AT25SF641B-MHB-T from Dialog Semiconductor/Adesto Adesto Technologies, in a UDFN-8(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select: a high-to-low transition starts an operation and a low-to-high transition ends it, and a 10k Ohm pull-up to VCC is recommended for power-up sequencing.
2 SO (IO1) bidirectional Serial data output clocked out on the falling edge of SCK, also I/O1 in dual and quad modes, and high-impedance when the device is deselected.
3 WP (IO2) bidirectional Write protect input (active low) protecting the Status Registers when QE=0 and SRP1/SRP0 = 0/1, or I/O2 when QE=1; internally pulled high and can be left floating if unused.
4 GND power_in Ground reference for the power supply, connected to system ground.
5 SI (IO0) bidirectional Serial data input for commands, addresses and data, latched on the rising edge of SCK, and I/O0 in dual and quad modes.
6 SCK input Serial clock input: command, address and input data are latched on the rising edge and output data is clocked out on the falling edge.
7 HOLD (IO3) bidirectional Pauses SPI communication without resetting the clocking sequence when QE=0, or I/O3 when QE=1; internally pulled high and can be left floating if unused.
8 VCC power_in Device power supply, 2.7 V to 3.6 V.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor/Adesto Adesto Technologies
Package UDFN-8(5x6)
Category Memory
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Deep Power-Down Current IDPD 1 5 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 52
Standby Current ISB 14 25 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 52
Active Current, Read (03h, 0Bh) ICC1 3 5 mA f = 20 MHz; IOUT = 0 52
Active Current, Read (03h, 0Bh) ICC1 4 6 mA f = 50 MHz; IOUT = 0 52
Active Current, Read (03h, 0Bh) ICC1 5 7.5 mA f = 85 MHz; IOUT = 0 52
Active Current, Read Dual (3Bh, BBh) ICC2 7 mA f = 50 MHz; IOUT = 0 52
Active Current, Read Dual (3Bh, BBh) ICC2 7 10 mA f = 85 MHz and 108 MHz; IOUT = 0 52
Active Current, Read Quad (6Bh, EBh) ICC3 6 9 mA f = 50 MHz; IOUT = 0 52
Active Current, Read Quad (6Bh, EBh) ICC3 9 13 mA f = 85 MHz and 108 MHz; IOUT = 0 52
Active Current, Program Operation ICC4 19 mA CS = VCC 52
Active Current, Erase Operation ICC5 15 mA CS = VCC 52
Input Load Current ILI -2 2 µA All inputs at CMOS levels 52
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 52
Input Low Voltage VIL -0.5 V 52
Output Low Voltage VOL 0.4 V IOL = 100 µA 52
Temperature under Bias -55 125 °C 52
Storage Temperature -65 150 °C 52
All Input Voltages (including NC Pins) -0.5 4 V with respect to Ground 52
All Output Voltages -0.5 V with respect to Ground; upper limit printed as VCC + 4.0 V 52
VCC Power Supply VCC 2.7 3.6 V 52
Operating Temperature (Case) -40 85 °C 52
Maximum Clock Frequency, all opcodes except 03h, 3Bh, 0Bh, 6Bh, EBh, E7h fCLK 104 MHz 2.7 V to 3.6 V 53
Maximum Clock Frequency, opcode EBh fCLK 104 MHz 2.7 V to 3.6 V 53
Maximum Clock Frequency, opcodes 0Bh, 3Bh, 6Bh, E7h fCLK 85 MHz 2.7 V to 3.6 V 53
Maximum Clock Frequency, opcode 03h fCLK 55 MHz 2.7 V to 3.6 V 53
Clock High Time tCLKH 4 ns 53
Clock Low Time tCLKL 4 ns 53
CS High Time tCSH 20 ns 53
CS Low Setup Time tCSLS 5 ns relative to Clock 53
CS Low Hold Time tCSLH 5 ns relative to Clock 53
CS High Setup Time tCSHS 5 ns relative to Clock 53
CS High Hold Time tCSHH 5 ns relative to Clock 53
Data In Setup Time tDS 2 ns 53
Data In Hold Time tDH 2 ns 53
Output Disable Time tDIS 6 ns 53
Output Valid Time tV 7 ns 53
Output Hold Time tOH 0 ns 53
HOLD Low to Output High-Z tHLQZ 6 ns 53
HOLD High to Output High-Z tHHQZ 6 ns 53
Write Protect Setup Time tWPS 20 ns 53
Write Protect Hold Time tWPH 100 ns 53
Page Program Time (256 Bytes) tPP 0.4 3 ms 2.7 V to 3.6 V 54
First Byte Program Time tBP1 30 50 µs 2.7 V to 3.6 V 54
Second Byte Program Time tBP2 2.5 12 µs 2.7 V to 3.6 V 54
Block Erase Time tBLKE 65 250 ms 4 kbytes 54
Block Erase Time tBLKE 150 500 ms 32 kbytes 54
Block Erase Time tBLKE 240 900 ms 64 kbytes 54
Chip Erase Time tCHPE 30 40 s 54
Write Status Register Time tWRSR 5 30 ms 54
Minimum VCC to Chip Select Low Time tVSL 70 µs 54

CAD (KiCad official)

  • Symbol: AT25SF641B-MHB-T
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: UDFN-8(5x6) (KiCad packages3D, STEP)
  • 3D model files: at25sf641b-mhb-t-etched.step / at25sf641b-mhb-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf641b-mhb-t.step / at25sf641b-mhb-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor/Adesto Adesto Technologies datasheet (61 pp, sha256 4e328b8bb228dfdd, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF