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AT25SF321B-SSHB-T

Public Made by Adom

by adom

RENESAS NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25SF321B-SSHB-T

RENESAS · NOR FLASH · SOIC-8

AT25SF321B-SSHB-T from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Asserting CS selects the device; a high-to-low transition is required to start an operation and a low-to-high transition is required to end it, and the device does not enter standby until an internally self-timed program or erase completes.
2 SO (IO1) bidirectional Serial data output clocked out on the falling edge of SCK, held high-impedance whenever the device is deselected, and used as I/O1 in dual-output read commands.
3 WP (IO2) bidirectional Write protect pin that controls the hardware locking feature; it is internally pulled high and may be left floating if hardware protection is unused, though connection to VCC is recommended, and it becomes I/O2 in quad commands.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SI (IO0) bidirectional Serial input for all data, command and address sequences, latched on the rising edge of SCK, ignored when the device is deselected, and used as I/O0 in dual- and quad-output reads.
6 SCK input Serial clock input: command, address and input data on SI are latched on the rising edge of SCK, and output data on SO is clocked out on the falling edge.
7 HOLD (IO3) bidirectional Pauses serial communication without deselecting or resetting the device while asserted (CS asserted and SCK low to start), with SO high-impedance; it is internally pulled high and may float if unused, though connection to VCC is recommended.
8 VCC power_in Device power supply pin that supplies the source voltage to the device.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Power Supply VCC 2.7 3.6 V 48
Operating Temperature (Case) Industrial -40 85 °C Industrial 48
Temperature under Bias -55 125 °C 48
Storage Temperature -65 150 °C 48
All Input Voltages (including NC Pins) with Respect to Ground -0.6 4.1 V 48
Deep Power-Down Current IDPD 1 3 µA CS, HOLD, WP = VIH; All inputs at CMOS levels 48
Standby Current ISB 13 25 µA CS, HOLD, WP = VIH; All inputs at CMOS levels 48
Active Current, Read (03h, 0Bh) Operation ICC1 3 4.2 mA f = 20 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.6 5.2 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 4.6 7.8 mA f = 85 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 4.6 6.4 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 6.4 8.8 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 5.6 8 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 8.2 12 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Program Operation ICC4 9 17 mA CS = VCC 48
Active Current, Erase Operation ICC5 7 11.5 mA CS = VCC 48
Input Load Current ILI -2 2 µA All inputs at CMOS levels 49
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 49
Input Low Voltage VIL -0.5 V 49
Output Low Voltage VOL 0.4 V IOL = 100 µA 49
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, 6Bh fCLK 108 MHz 2.7 V to 3.6 V 49
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh fCLK1 85 MHz 2.7 V to 3.6 V 49
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 2.7 V to 3.6 V 49
Clock High Time tCLKH 4 ns 2.7 V to 3.6 V 49
Clock Low Time tCLKL 4 ns 2.7 V to 3.6 V 49
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 2.7 V to 3.6 V 49
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLK 0.1 V/ns 2.7 V to 3.6 V 49
CS High Time tCSH 20 ns 2.7 V to 3.6 V 49
CS Low Setup Time (relative to Clock) tCSLS 5 ns 2.7 V to 3.6 V 49
CS Low Hold Time (relative to Clock) tCSLH 5 ns 2.7 V to 3.6 V 49
CS High Setup Time (relative to Clock) tCSHS 5 ns 2.7 V to 3.6 V 49
CS High Hold Time (relative to Clock) tCSHH 5 ns 2.7 V to 3.6 V 49
Data In Setup Time tDS 2 ns 2.7 V to 3.6 V 49
Data In Hold Time tDH 2 ns 2.7 V to 3.6 V 50
Output Disable Time tDIS 6 ns 2.7 V to 3.6 V 50
Output Valid Time tV 7 ns 2.7 V to 3.6 V 50
Output Hold Time tOH 0 ns 2.7 V to 3.6 V 50
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 2.7 V to 3.6 V 50
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 2.7 V to 3.6 V 50
HOLD High Setup Time (relative to Clock) tHHS 5 ns 2.7 V to 3.6 V 50
HOLD High Hold Time (relative to Clock) tHHH 5 ns 2.7 V to 3.6 V 50
HOLD Low to Output High-Z tHLQZ 6 ns 2.7 V to 3.6 V 50
HOLD High to Output High-Z tHHQZ 6 ns 2.7 V to 3.6 V 50
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 2.7 V to 3.6 V 50
CS High to Standby Mode With Electronic Signature Read tRES2 20 µs 2.7 V to 3.6 V 50
CS High to Next Instruction After Suspend tSUS 20 µs 2.7 V to 3.6 V 50
Write Protect Setup Time tWPS 20 ns 2.7 V to 3.6 V 50
Write Protect Hold Time tWPH 100 ns 2.7 V to 3.6 V 50
CS High to Deep Power-Down tEDPD 20 µs 2.7 V to 3.6 V 50
CS High to Standby Mode tRDPD 20 µs 2.7 V to 3.6 V 50
Minimum VCC to Chip Select Low Time tVCSL 70 µs 51
Page Program Time (256 Bytes) tPP 0.4 3.4 ms 2.7 V to 3.6 V 50
First Byte Program Time tBP1 30 50 µs 2.7 V to 3.6 V 50
Second Byte Program Time tBP2 2.5 12 µs 2.7 V to 3.6 V 50
Block Erase Time 4 kbytes tBLKE 55 250 ms 2.7 V to 3.6 V 50
Block Erase Time 32 kbytes tBLKE 120 450 ms 2.7 V to 3.6 V 50
Block Erase Time 64 kbytes tBLKE 200 700 ms 2.7 V to 3.6 V 50
Chip Erase Time tCHPE 10 30 sec 2.7 V to 3.6 V 50
Write Status Register Time tWRSR 5 30 ms 2.7 V to 3.6 V 50
All Output Voltages with Respect to Ground -0.6 V 48

CAD (KiCad official)

  • Symbol: AT25SF321B-SSHB-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25sf321b-sshb-t-etched.step / at25sf321b-sshb-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf321b-sshb-t.step / at25sf321b-sshb-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (59 pp, sha256 fa5eb65e69b476b2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF