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Contents

README

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AT25SF321B-SSHB-B

Adesto Technologies · Pre-ordered Chips · SOIC-8

AT25SF321B-SSHB-B from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input CHIP SELECT, active low; a high-to-low transition starts an operation and a low-to-high transition ends it.
2 SO (I/O1) bidirectional SERIAL OUTPUT, clocked out on the falling edge of SCK and high-impedance whenever the device is deselected; acts as I/O1 in Dual and Quad read commands.
3 WP (I/O2) bidirectional WRITE PROTECT, internally pulled high and may be left floating if hardware protection is unused; recommended to be connected to VCC whenever possible; acts as I/O2 in Quad commands.
4 GND power_in GROUND, the ground reference for the power supply; connect to system ground.
5 SI (I/O0) bidirectional SERIAL INPUT, latched on the rising edge of SCK for all command, address and data input; acts as I/O0 in Dual and Quad commands and is ignored when the device is deselected.
6 SCK input SERIAL CLOCK, providing the clock to the device; SI is latched on the rising edge and SO is clocked out on the falling edge.
7 HOLD (I/O3) bidirectional HOLD, temporarily pauses serial communication without deselecting or resetting the device while asserted; internally pulled high and recommended to be connected to VCC whenever possible; acts as I/O3 in Quad commands.
8 VCC power_in DEVICE POWER SUPPLY, single 2.7 V to 3.6 V supply input.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TSTG -65 150 °C 48
Temperature under Bias -55 125 °C 48
All Input Voltages with Respect to Ground -0.6 4.1 V including NC pins 48
All Output Voltages with Respect to Ground -0.6 V VCC + 0.5 V maximum 48
Operating Temperature (Case) Industrial -40 85 °C 48
VCC Power Supply VCC 2.7 3.6 V 48
Deep Power-Down Current IDPD 1 3 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Standby Current ISB 13 25 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Active Current, Read (03h, 0Bh) Operation ICC1 3 4.2 mA f = 20 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.6 5.2 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 4.6 7.8 mA f = 85 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 4.6 6.4 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 6.4 8.8 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 5.6 8 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 8.2 12 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Program Operation ICC4 9 17 mA CS = VCC 48
Active Current, Erase Operation ICC5 7 11.5 mA CS = VCC 48
Input Load Current ILI -2 2 µA All inputs at CMOS levels 49
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 49
Input Low Voltage VIL -0.5 V 49
Output Low Voltage VOL 0.4 V IOL = 100 µA 49
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, 6Bh fCLK 108 MHz 49
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh fCLK1 85 MHz 49
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 49
Clock High Time tCLKH 4 ns 49
Clock Low Time tCLKL 4 ns 49
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 49
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLK 0.1 V/ns 49
CS High Time tCSH 20 ns 49
CS Low Setup Time (relative to Clock) tCSLS 5 ns 49
CS Low Hold Time (relative to Clock) tCSLH 5 ns 49
CS High Setup Time (relative to Clock) tCSHS 5 ns 49
CS High Hold Time (relative to Clock) tCSHH 5 ns 49
Data In Setup Time tDS 2 ns 49
Data In Hold Time tDH 2 ns 49
Output Disable Time tDIS 6 ns 50
Output Valid Time tV 7 ns 50
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 50
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 50
HOLD High Setup Time (relative to Clock) tHHS 5 ns 50
HOLD Low to Output High-Z tHLQZ 6 ns 50
HOLD High to Output High-Z tHHQZ 6 ns 50
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 50
CS High to Standby Mode With Electronic Signature Read tRES2 20 µs 50
CS High to Next Instruction After Suspend tSUS 20 µs 50
Write Protect Setup Time tWPS 20 ns 50
Write Protect Hold Time tWPH 100 ns 50
CS High to Deep Power-Down tEDPD 20 µs 50
CS High to Standby Mode tRDPD 20 µs 50
Resume Deep Power-Down, CS High to ID tRDPO 20 µs 50
Minimum VCC to Chip Select Low Time tVCSL 70 µs 51
Page Program Time (256 Bytes) tPP 0.4 3.4 ms 50
First Byte Program Time tBP1 30 50 µs 50
Second Byte Program Time tBP2 2.5 12 µs 50
Block Erase Time 4 kbytes tBLKE 55 250 ms 4 kbytes 50
Block Erase Time 32 kbytes tBLKE 120 450 ms 32 kbytes 50
Block Erase Time 64 kbytes tBLKE 200 700 ms 64 kbytes 50
Chip Erase Time tCHPE 10 30 sec 50
Write Status Register Time tWRSR 5 30 ms 50

CAD (KiCad official)

  • Symbol: AT25SF321B-SSHB-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25sf321b-sshb-b-etched.step / at25sf321b-sshb-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf321b-sshb-b.step / at25sf321b-sshb-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (59 pp, sha256 a3be84cdc8f2d5a0, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF