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AT25SF161B-SSHD-B

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RENESAS NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25SF161B-SSHD-B

RENESAS · NOR FLASH · SOIC-8

AT25SF161B-SSHD-B from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select; a high-to-low transition starts an operation, a low-to-high transition ends it, and the device is deselected and normally in standby when deasserted.
2 SO (IO1) bidirectional Serial output clocked out on the falling edge of SCK (I/O1 in Dual/Quad modes); high-impedance when the device is deselected.
3 WP (IO2) bidirectional Write protect for hardware locking, becoming I/O2 in Quad commands; internally pulled high, can be left floating if unused, but connecting to VCC is recommended.
4 GND power_in Ground reference for the power supply; connect to system ground.
5 SI (IO0) bidirectional Serial input for commands, addresses and data latched on the rising edge of SCK, and becomes I/O0 in Dual/Quad output modes; ignored when deselected.
6 SCK input Serial clock; command, address and input data on SI are latched on the rising edge and output data on SO is clocked out on the falling edge.
7 HOLD (IO3) bidirectional Pauses serial communication without deselecting the device, becoming I/O3 in Quad commands; internally pulled high, can be left floating if unused, but connecting to VCC is recommended.
8 VCC power_in Device power supply; operating range is 2.5 V to 3.6 V for the -SSHD option.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under Bias -55 125 °C 52
Storage Temperature -65 150 °C 52
All Input Voltages (including NC pins) with respect to Ground -0.5 4 V 52
All Output Voltages with respect to Ground -0.6 V max printed as VCC + 0.5 V 52
Operating Temperature (Case) -40 85 °C Industrial 52
VCC Power Supply VCC 2.5 3.6 V 52
Deep Power-Down Current IDPD 1.5 10 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 52
Standby Current ISB 15 30 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 52
Active Current, Read (03h, 0Bh) ICC1 4 5 mA f = 20 MHz; IOUT = 0 52
Active Current, Read (03h, 0Bh) ICC1 4.5 6 mA f = 50 MHz; IOUT = 0 52
Active Current, Read (03h, 0Bh) ICC1 5.5 7 mA f = 85 MHz; IOUT = 0 52
Active Current, Read Operation (Dual) (3Bh, BBh) ICC2 5.5 7 mA f = 50 MHz; IOUT = 0 52
Active Current, Read Operation (Dual) (3Bh, BBh) ICC2 7.5 10 mA f = 85 MHz and 104 MHz; IOUT = 0 52
Active Current, Read Operation (Quad) (6Bh, EBh) ICC3 7 9 mA f = 50 MHz; IOUT = 0 52
Active Current, Read Operation (Quad) (6Bh, EBh) ICC3 10 13 mA f = 85 MHz and 104 MHz; IOUT = 0 52
Active Current, Program Operation ICC4 20 mA CS = VCC 52
Active Current, Erase Operation ICC5 14 mA CS = VCC 52
Input Load Current ILI -2 2 µA All inputs at CMOS levels 52
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 52
Output Low Voltage VOL 0.4 V IOL = 100 µA 52
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, and 6Bh fCLK 108 MHz 53
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh fCLK1 85 MHz 53
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 53
Clock High Time tCLKH 4 ns 53
Clock Low Time tCLKL 4 ns 53
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns Not 100% tested; guaranteed by design and characterization 53
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns Not 100% tested; guaranteed by design and characterization 53
CS High Time tCSH 20 ns 53
CS Low Setup Time (relative to Clock) tCSLS 5 ns 53
CS Low Hold Time (relative to Clock) tCSLH 5 ns 53
CS High Setup Time (relative to Clock) tCSHS 5 ns 53
CS High Hold Time (relative to Clock) tCSHH 5 ns 53
Data In Setup Time tDS 2 ns 53
Data In Hold Time tDH 2 ns 53
Output Disable Time tDIS 6 ns Not 100% tested; guaranteed by design and characterization 53
Output Valid Time tV 7 ns 53
Output Hold Time tOH 0 ns 53
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 53
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 53
HOLD High Setup Time (relative to Clock) tHHS 5 ns 53
HOLD High Hold Time (relative to Clock) tHHH 5 ns 53
HOLD Low to Output High-Z tHLQZ 6 ns Not 100% tested; guaranteed by design and characterization 53
HOLD High to Output High-Z tHHQZ 6 ns Not 100% tested; guaranteed by design and characterization 53
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 53
CS High to Next Instruction After Suspend tSUS 20 µs 53
Write Protect Setup Time tWPS 20 ns Not 100% tested; guaranteed by design and characterization 53
Write Protect Hold Time tWPH 100 ns Not 100% tested; guaranteed by design and characterization 53
CS High to Deep Power-Down tEDPD 20 µs 53
CS High to Standby Mode tRDPD 20 µs 53
Resume Deep Power-Down, CS High to ID tRDPO 20 µs 53
Page Program Time (256 Bytes) tPP 0.4 1.8 ms 54
First Byte Program Time tBP1 30 50 µs 54
Second Byte Program Time tBP2 2.5 12 µs 54
Block Erase Time tBLKE 50 220 ms 4 kbyte 54
Block Erase Time tBLKE 120 450 ms 32 kbyte 54
Block Erase Time tBLKE 200 700 ms 64 kbyte 54
Chip Erase Time tCHPE 5.5 11 s Max spec based on limited endurance cycle 54
Write Status Register Time tWRSR 5 30 ms 54
Minimum VCC to Chip Select Low Time tVCSL 70 µs 54

CAD (KiCad official)

  • Symbol: AT25SF161B-SSHD-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25sf161b-sshd-b-etched.step / at25sf161b-sshd-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf161b-sshd-b.step / at25sf161b-sshd-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (64 pp, sha256 37b26a23558c5916, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF