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AT25SF041B-SSHD-T

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Dialog Semiconductor NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25SF041B-SSHD-T

Dialog Semiconductor · NOR FLASH · SOIC-8

AT25SF041B-SSHD-T from Dialog Semiconductor, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input CHIP SELECT: Asserting the CS pin selects the device, and a high-to-low transition is required to start an operation while a low-to-high transition ends it.
2 SO (IO1) bidirectional SERIAL OUTPUT: Data on the SO pin is clocked out on the falling edge of SCK, and the pin is high-impedance whenever the device is deselected.
3 WP (IO2) bidirectional WRITE PROTECT: The WP pin controls the hardware locking feature and is internally pulled high, with external connection to VCC recommended whenever possible.
4 GND power_in GROUND: The ground reference for the power supply, which must be connected to the system ground.
5 SI (IO0) bidirectional SERIAL INPUT: Data on the SI pin is always latched in on the rising edge of SCK and is ignored whenever the device is deselected.
6 SCK input SERIAL CLOCK: This pin provides the clock to the device, latching SI input on the rising edge and clocking SO output on the falling edge.
7 HOLD (IO3) bidirectional HOLD: The HOLD pin temporarily pauses serial communication without deselecting or resetting the device, and is internally pulled high with external connection to VCC recommended whenever possible.
8 VCC power_in DEVICE POWER SUPPLY: The VCC pin supplies the source voltage to the device, specified as 2.7 V to 3.6 V for this ordering code.

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Case) -40 85 °C Industrial 48
VCC Power Supply VCC 2.5 3.6 V 2.5 V to 3.6 V device 48
Temperature under Bias -55 125 °C 48
Storage Temperature -65 150 °C 48
All Input Voltages (including NC Pins) with Respect to Ground -0.5 4 V 48
All Output Voltages with Respect to Ground -0.6 V max VCC + 0.5 V 48
Deep Power-Down Current IDPD 1.2 11 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Standby Current ISB 13.3 30 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.3 4.7 mA f = 20 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.8 5.4 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 4.5 6.5 mA f = 85 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 4.8 6.7 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 6.2 8.8 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 5.7 8.2 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 7.6 11.2 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Program Operation ICC4 11 18.5 mA CS = VCC 48
Active Current, Erase Operation ICC5 7 12 mA CS = VCC 48
Input Load Current ILI -2 2 µA All inputs at CMOS levels 48
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 48
Output Low Voltage VOL 0.4 V IOL = 100 µA 48
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, and 6Bh fCLK 108 MHz 49
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh fCLK1 85 MHz 49
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 49
Clock High Time tCLKH 4 ns 49
Clock Low Time tCLKL 4 ns 49
CS High Time tCSH 20 ns 49
CS Low Setup Time (relative to Clock) tCSLS 5 ns 49
CS Low Hold Time (relative to Clock) tCSLH 5 ns 49
CS High Setup Time (relative to Clock) tCSHS 5 ns 49
CS High Hold Time (relative to Clock) tCSHH 5 ns 49
Data In Setup Time tDS 2 ns 49
Data In Hold Time tDH 2 ns 49
Output Disable Time tDIS 6 ns 49
Output Valid Time tV 7 ns 49
Output Hold Time tOH 0 ns 49
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 49
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 49
HOLD High Setup Time (relative to Clock) tHHS 5 ns 49
HOLD High Hold Time (relative to Clock) tHHH 5 ns 49
HOLD Low to Output High-Z tHLQZ 6 ns 49
HOLD High to Output High-Z tHHQZ 6 ns 49
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 49
CS High to Next Instruction After Suspend tSUS 20 µs 49
Write Protect Setup Time tWPS 20 ns 49
Write Protect Hold Time tWPH 100 ns 49
CS High to Standby Mode tRDPD 20 µs 49
Page Program Time (256 Bytes) tPP 0.4 0.8 ms 50
First Byte Program Time tBP1 30 50 µs 50
Second Byte Program Time tBP2 2.5 12 µs 50
Block Erase Time 4 kbytes tBLKE 60 90 ms 50
Block Erase Time 32 kbytes tBLKE 135 210 ms 50
Block Erase Time 64 kbytes tBLKE 220 360 ms 50
Chip Erase Time tCHPE 1.5 3 sec 50
Write Status Register Time tWRSR 5 30 ms 50
Minimum VCC to Chip Select Low Time tVCSL 70 µs 50

CAD (KiCad official)

  • Symbol: AT25SF041B-SSHD-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25sf041b-sshd-t-etched.step / at25sf041b-sshd-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf041b-sshd-t.step / at25sf041b-sshd-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor datasheet (58 pp, sha256 6c844d456310075d, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF