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AT25SF041B-MHB-T

Dialog Semiconductor/Adesto Adesto Technologies · NOR FLASH · UDFN-8(5x6)

AT25SF041B-MHB-T from Dialog Semiconductor/Adesto Adesto Technologies, in a UDFN-8(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select: a high-to-low transition starts an operation and a low-to-high transition ends it, and a 10k pull-up to VCC is recommended for power-up sequencing.
2 SO (IO1) bidirectional Serial data output clocked out on the falling edge of SCK, also IO1 in dual/quad modes, and high-impedance when the device is deselected.
3 WP (IO2) bidirectional Write-protect input (active low) when QE=0 and SRP1/SRP0 = 0/1, or IO2 when QE=1; internally pulled high and can be left floating if unused.
4 GND power_in Ground reference for the power supply; connect to system ground.
5 SI (IO0) bidirectional Serial data input for commands, addresses and data, latched on the rising edge of SCK, and becomes IO0 for dual/quad commands.
6 SCK input Serial clock: input on SI is latched on the rising edge and output on SO is clocked out on the falling edge.
7 HOLD (IO3) bidirectional Pauses SPI communication without resetting the clock sequence when QE=0 (CS must be low), or acts as IO3 when QE=1; internally pulled high and can be left floating if unused.
8 VCC power_in Device power supply, 2.7 V to 3.6 V or 2.5 V to 3.6 V depending on ordering option.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor/Adesto Adesto Technologies
Package UDFN-8(5x6)
Category Memory
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under Bias -55 125 °C 50
Storage Temperature -65 150 °C 50
All Input Voltages (including NC Pins) with Respect to Ground -0.5 4 V 50
All Output Voltages with Respect to Ground (lower limit) -0.6 V upper limit VCC + 0.5 V 50
Operating Temperature (Case) -40 85 °C 50
VCC Power Supply VCC 2.7 3.6 V B = 2.7 V - 3.6 V device 50
Deep Power-Down Current IDPD 1.2 11 µA CS, HOLD, WP = VIH; All inputs at CMOS levels 50
Standby Current ISB 13.3 30 µA CS, HOLD, WP = VIH; All inputs at CMOS levels 50
Active Current, Read (03h, 0Bh) ICC1 3.3 4.7 mA f = 20 MHz; IOUT = 0 50
Active Current, Read (03h, 0Bh) ICC1 3.8 5.4 mA f = 50 MHz; IOUT = 0 50
Active Current, Read (03h, 0Bh) ICC1 4.5 6.5 mA f = 85 MHz; IOUT = 0 50
Active Current, Read Operation (Dual) (3Bh, BBh) ICC2 4.8 6.7 mA f = 50 MHz; IOUT = 0 50
Active Current, Read Operation (Dual) (3Bh, BBh) ICC2 6.2 8.8 mA f = 85 MHz and 108 MHz; IOUT = 0 50
Active Current, Read Operation (Quad) (6Bh, EBh) ICC3 5.7 8.2 mA f = 50 MHz; IOUT = 0 50
Active Current, Read Operation (Quad) (6Bh, EBh) ICC3 7.6 12 mA f = 85 MHz and 108 MHz; IOUT = 0 50
Active Current, Program Operation ICC4 11 16 mA CS = VCC 50
Active Current, Erase Operation ICC5 7 12 mA CS = VCC 50
Input Load Current ILI -2 2 µA All inputs at CMOS levels 50
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 50
Output Low Voltage VOL 0.4 V IOL = 100 µA 50
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, and 6Bh fCLK 108 MHz 51
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh fCLK1 85 MHz 51
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 51
Clock High Time tCLKH 4 ns 51
Clock Low Time tCLKL 4 ns 51
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 51
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns 51
CS High Time tCSH 20 ns 51
CS Low Setup Time (relative to Clock) tCSLS 5 ns 51
CS Low Hold Time (relative to Clock) tCSLH 5 ns 51
CS High Setup Time (relative to Clock) tCSHS 5 ns 51
CS High Hold Time (relative to Clock) tCSHH 5 ns 51
Data In Setup Time tDS 2 ns 51
Data In Hold Time tDH 2 ns 51
Output Disable Time tDIS 6 ns 51
Output Valid Time tV 7.5 ns 51
Output Hold Time tOH 0 ns 51
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 51
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 51
HOLD High Setup Time (relative to Clock) tHHS 5 ns 51
HOLD High Hold Time (relative to Clock) tHHH 5 ns 51
HOLD Low to Output High-Z tHLQZ 6 ns 51
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 51
CS High to Standby Mode With Electronic Signature Read tRES2 20 µs 51
CS High to Next Command After Suspend tSUS 20 µs 51
Write Protect Setup Time tWPS 20 ns 51
Write Protect Hold Time tWPH 100 ns 51
CS High to Deep Power-Down tEDPD 20 µs 51
CS High to Standby Mode tRDPD 20 µs 51
Resume Deep Power-Down, CS High to ID tRDPO 20 µs 51
Page Program Time (256 Bytes) tPP 0.4 2 ms 52
First Byte Program Time tBP1 30 50 µs 52
Second Byte Program Time tBP2 2.5 12 µs 52
Block Erase Time tBLKE 60 200 ms 4 kbytes 52
Block Erase Time tBLKE 120 300 ms 32 kbytes 52
Block Erase Time tBLKE 200 400 ms 64 kbytes 52
Chip Erase Time tCHPE 1.5 3 sec 52
Write Status Register Time tWRSR 5 30 ms 52
Minimum VCC to Chip Select Low Time tVSL 70 µs 52

CAD (KiCad official)

  • Symbol: AT25SF041B-MHB-T
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: UDFN-8(5x6) (KiCad packages3D, STEP)
  • 3D model files: at25sf041b-mhb-t-etched.step / at25sf041b-mhb-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf041b-mhb-t.step / at25sf041b-mhb-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor/Adesto Adesto Technologies datasheet (60 pp, sha256 f21609cd0e2ce4d1, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF