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AT25PE80-SSHN-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat25pe80-sshn-tfactory-2.0.0extractor-text

Verified AT25PE80-SSHN-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT25PE80-SSHN-T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 62-page datasheet
  • ✓distributor: lcsc C2061696, digikey 1265-1328-2-ND, mouser 988-AT25PE80-SSHN-T
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g8d2e158/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.58)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at25pe80-sshn-t.kicad_sym✓ at25pe80-sshn-t.kicad_mod✓ at25pe80-sshn-t.step
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Ray Publish 0.1.0 cb035f1 4h ago

AT25PE80-SSHN-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25PE80-SSHN-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select, active low: asserting CS selects the device, and deasserting it deselects the device, places it in standby (not Deep Power-Down), forces SO to high impedance, and causes SI to be ignored.
2 SO output Serial Output: data is clocked out on the falling edge of SCK, and the pin is high impedance whenever the device is deselected (CS deasserted).
3 WP input Write Protect, active low: when asserted, sectors listed in the Sector Protection Register are protected against program and erase, and program/erase commands are ignored; the pin is internally pulled high and should preferably be connected to VCC.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SI input Serial Input for all command, address and data input, latched on the rising edge of SCK and ignored whenever the device is deselected.
6 SCK input Serial Clock: command, address and input data on SI are latched on the rising edge, and output data on SO is clocked out on the falling edge.
7 RESET input Active-low reset: a low level terminates the operation in progress and returns the internal state machine to idle while held low; if the feature is unused it should be driven high externally.
8 VCC power_in Device power supply pin; the device operates from a single 1.7V to 3.6V supply, and operation at invalid VCC voltages may produce spurious results.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.4 1 µA CS= VCC. All other inputs at 0V or VCC 41
Deep Power-Down Current IDPD 4.5 12 µA CS= VCC. All other inputs at 0V or VCC 41
Standby Current ISB 25 40 µA CS= VCC. All other inputs at 0V or VCC 41
Active Current, Low Power Read (01h) Operation ICC1 6 9 mA f = 1MHz; IOUT = 0mA 41
Active Current, Low Power Read (01h) Operation ICC1 7 10 mA f = 15MHz; IOUT = 0mA 41
Active Current, Read Operation ICC2 10 12 mA f = 50MHz; IOUT = 0mA 41
Active Current, Read Operation ICC2 12 15 mA f = 85MHz; IOUT = 0mA 41
Active Current, Program Operation ICC3 14 16 mA CS = VCC 41
Active Current, Erase Operation ICC4 8 12 mA CS = VCC 41
Input Load Current ILI 1 µA All inputs at CMOS levels 41
Output Leakage Current ILO 1 µA All inputs at CMOS levels 41
Input Low Voltage VIL 0.3 ×VCC Printed as VCC x 0.3; min cell blank 41
Input High Voltage VIH 0.7 ×VCC Printed as VCC x 0.7 (min) 41
Input High Voltage VIH 0.6 V above VCC Printed as VCC + 0.6 (max) 41
Output Low Voltage VOL 0.4 V IOL = 100µA 41
Output High Voltage VOH 0.2 V below VCC IOH = -100µA; printed as VCC - 0.2V (min) 41
SCK Frequency fSCK 85 MHz 1.7V to 3.6V column 42
SCK Frequency for Continuous Read (0x0B) fCAR1 85 MHz 1.7V to 3.6V column 42
SCK Frequency for Continuous Read (0x03) (Low Frequency) fCAR2 50 MHz 1.7V to 3.6V column 42
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode) fCAR3 20 MHz 1.7V to 3.6V column 42
SCK Frequency for Continuous Read (0x1B) fCAR4 85 MHz 1.7V to 3.6V column 42
SCK High Time tWH 4 ns 1.7V to 3.6V column 42
SCK Low Time tWL 4 ns 1.7V to 3.6V column 42
SCK Rise Time, Peak-to-peak tSCKR 0.1 V/ns Characterized, not 100% tested 42
SCK Fall Time, Peak-to-peak tSCKF 0.1 V/ns Characterized, not 100% tested 42
Minimum CS High Time tCS 30 ns 42
CS Setup Time tCSS 6 ns 1.7V to 3.6V column 42
CS Hold Time tCSH 5 ns 1.7V to 3.6V column 42
Data In Setup Time tSU 2 ns 1.7V to 3.6V column 42
Data In Hold Time tH 1 ns 1.7V to 3.6V column 42
Output Hold Time tHO 0 ns 1.7V to 3.6V column 42
Output Disable Time tDIS 8 ns Characterized, not 100% tested; 1.7V to 3.6V column 42
Output Valid tV 7 ns 1.7V to 3.6V column 42
WP Low to Protection Enabled tWPE 1 µs 1.7V to 3.6V column 42
WP High to Protection Disabled tWPD 1 µs 1.7V to 3.6V column 42
CS High to Ultra-Deep Power-Down tEUDPD 3 µs Characterized, not 100% tested 42
Minimum CS Low Time to Exit Ultra-Deep Power-Down tCSLU 20 ns 1.7V to 3.6V column 42
Exit Ultra-Deep Power-Down Time tXUDPD 100 µs 1.7V to 3.6V column 42
CS High to Deep Power-Down tEDPD 3 µs Characterized, not 100% tested 42
Resume from Deep Power-Down Time tRDPD 35 µs 1.7V to 3.6V column 42
Page to Buffer Transfer Time tXFR 200 µs 1.7V to 3.6V column 42
Page to Buffer Compare Time tCOMP 200 µs 1.7V to 3.6V column 42
RESET Pulse Width tRST 10 µs 1.7V to 3.6V column 42
RESET Recovery Time tREC 1 µs 1.7V to 3.6V column 42
Software Reset Time tSWRST 50 µs 1.7V to 3.6V column 42
Page Erase and Programming Time (256/264 bytes) tEP 15 55 ms 1.7V to 3.6V column 43
Page Programming Time tP 2 4 ms 1.7V to 3.6V column 43
Page Erase Time tPE 12 50 ms 1.7V to 3.6V column 43
Block Erase Time tBE 30 75 ms 1.7V to 3.6V column 43
Sector Erase Time tSE 0.7 1.3 s 1.7V to 3.6V column 43
Chip Erase Time tCE 10 20 s 1.7V to 3.6V column 43
Byte Programming Time tBP 8 µs 1.7V to 3.6V column; single value, placed in typ 43
Output Voltages with Respect to Ground -0.6 4.2 V Max VCC of 3.6V + 0.6V 40
Input Voltages with Respect to Ground -0.6 4.2 V Excluding VCC pin, including NC pins; max VCC of 3.6V + 0.6V 40
Storage Temperature -65 150 °C 40
Temperature under Bias -55 125 °C 40
Operating Temperature (Case) Industrial -40 85 °C Case, industrial grade 40
VCC Power Supply VCC 1.7 3.6 V 40

CAD (KiCad official)

  • Symbol: AT25PE80-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25pe80-sshn-t-etched.step / at25pe80-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25pe80-sshn-t.step / at25pe80-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (62 pp, sha256 ffe00f4808a37652, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF