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AT25FF161A-SSHN-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat25ff161a-sshn-tfactory-2.0.0extractor-text

Verified AT25FF161A-SSHN-T

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT25FF161A-SSHN-T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 118-page datasheet
  • ✓distributor: lcsc C1857758, digikey 1265-AT25FF161A-SSHN-TTR-ND, mouser 724-AT25FF161ASSHNT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jscamqwf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at25ff161a-sshn-t.kicad_sym✓ at25ff161a-sshn-t.kicad_mod✓ at25ff161a-sshn-t.step
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AT25FF161A-SSHN-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25FF161A-SSHN-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select, active low: asserting CS selects the device, and a high-to-low transition is required to start an operation while a low-to-high transition ends it.
2 SO (I/O1) bidirectional Serial output clocked out on the falling edge of SCK, becoming I/O1 in multi-I/O read modes and high-impedance when the device is deselected.
3 WP (I/O2) bidirectional Write protect input, internally pulled high and recommended to be connected to VCC, becoming I/O2 when the QE bit is set.
4 GND power_in Ground reference for the power supply; should be connected to the system ground.
5 SI (I/O0) bidirectional Serial input latched on the rising edge of SCK, becoming I/O0 in multi-I/O read modes and ignored while the device is deselected.
6 SCK input Serial clock: command, address and input data on SI are latched on the rising edge, and output data on SO is clocked out on the falling edge.
7 HOLD/RESET (I/O3) bidirectional Pauses serial communication while asserted with CS low, or acts as a device RESET per Status Register 3 bit 7, internally pulled high and becoming I/O3 when QE is set.
8 VCC power_in Supplies the source voltage to the device; operation at invalid VCC voltages may produce spurious results and should not be attempted.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under bias -55 125 °C 104
Storage Temperature -65 150 °C 104
All input voltages (including NC pins) with respect to ground -0.6 V 104
All output voltages with respect to ground -0.6 V 104
Operating Temperature (Case) -40 85 °C 104
VCC Power Supply VCC 1.65 3.6 V 104
Ultra-Deep Power-Down Current IUDPD 5 7 250 nA CS = VCC. All other inputs at 0V or VCC 104
Deep Power-Down Current IDPD 6 13 µA CS, RESET, WP = VCC. All other inputs at 0V or VCC 104
Standby Current ISB 24 50 µA CS, RESET, WP = VCC. All other inputs at 0V or VCC 104
Active Current, SPI (33 MHz) ICC1 5.1 6.9 mA IOUT = 0mA 104
Active Current, SPI (104 MHz) ICC1 7.6 12 mA IOUT = 0mA 104
Active Current, Dual (104 MHz) ICC1 11 12.4 mA IOUT = 0mA 104
Active Current, Quad (104 MHz) ICC1 11.8 14.6 mA IOUT = 0mA 104
Active Current, Program Operation ICC3 8.6 11 mA CS = VCC 104
Active Current, Erase Operation ICC4 9.3 12 mA CS = VCC 104
Input Load Current ILI -2 2 µA All inputs at CMOS levels 104
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 104
Output Low Voltage VOL 0.2 V IOL = 100 µA 105
Maximum clock frequency for all operations (except 03h command) fSCK 104 MHz Except 03h command 105
Maximum clock frequency for 03h command (Read Array, Low Frequency) fRDLF 40 MHz 03h command 105
SCK High Time tCLKH 4.5 ns 105
SCK Low Time tCLKL 4.5 ns 105
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.75 V/ns 105
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.75 V/ns 105
Minimum CS High Time tCSH 35 ns 105
CS Low Setup Time (relative to clock) tCSLS 6 ns 105
CS Low Hold Time (relative to clock) tCSLH 6 ns 105
CS High Setup Time (relative to clock) tCSHS 6 ns 105
CS High Hold Time (relative to clock) tCSHH 6 ns 105
Data In Setup Time tDS 2 ns 105
Data In Hold Time tDH 1 ns 105
Output Disable Time tDIS 8 ns 106
Output Valid Time tV 8 ns 106
Output Hold Time tOH 0 ns 106
HOLD Low Setup Time (relative to clock) tHLS 6 ns 106
HOLD Low Hold Time (relative to clock) tHLH 6 ns 106
HOLD High Setup Time (relative to clock) tHHS 6 ns 106
HOLD High Hold Time (relative to clock) tHHH 6 ns 106
HOLD Low to Output High-Z tHLQZ 7 ns 106
HOLD High to Output Low-Z tHHQX 7 ns 106
Write Protect Setup Time tWPS 20 ns 106
Write Protect Hold Time tWPH 100 ns 106
CS High to Deep Power-Down tEDPD 3 µs 106
CS High to Ultra Deep Power-Down tEUDPD 3 µs 106
Return from Terminate Command Time tSWSTOP 50 µs 106
Resume from Software Reset Time tSWRST 260 µs 106
Resume from Ultra Deep Power-Down Time tRUDPD 160 260 µs Max valid for UDPD hold time >400 ms 106
Resume from Deep Power-Down Time tRDPD 35 µs 106
Page Program Time (256 Bytes) tPP 1.5 8 ms 256 Bytes 106
Block Erase Time, 4 KBytes tBLKE 66 115 ms 4 KBytes 106
Block Erase Time, 32 KBytes tBLKE 515 800 ms 32 KBytes 106
Block Erase Time, 64 KBytes tBLKE 800 1600 ms 64 KBytes 106
Resume Time (Program) tRES 8 10 µs 107
Resume Time (Erase) tRES 8 10 µs 107
OTP Security Register Program Time tOTPP 5 6 ms <= 10K 107
Write Status Register Time tWRSR 13 37 ms 107
Minimum VCC to full operation permitted tVCSL 260 µs 108
VCC rise time (from 0V to VCCmin) tVR 1 30000 µs/V 108
VCC brown-out low time tPWD 300 µs 108
Maximum VCC brown-out VPWDMAX 0.2 V 108

CAD (KiCad official)

  • Symbol: AT25FF161A-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25ff161a-sshn-t-etched.step / at25ff161a-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25ff161a-sshn-t.step / at25ff161a-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (118 pp, sha256 07456103873d2514, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF