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AT25DN512C-SSHF-T

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Dialog Semiconductor Adesto Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT25DN512C-SSHF-T

Dialog Semiconductor Adesto Adesto Technologies · NOR FLASH · SOIC-8

AT25DN512C-SSHF-T from Dialog Semiconductor Adesto Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select, active low: asserting CS selects the device, a high-to-low transition starts an operation and a low-to-high transition ends it, and SO is high-impedance while CS is deasserted.
2 SO (I/O1) bidirectional Serial output that shifts data out on the falling edge of SCK, and it becomes I/O1 in the Dual-Output Read commands; it is high-impedance whenever the device is deselected.
3 WP input Write protect input that controls hardware locking of protected sectors, is internally pulled high and may be left floating, though it is recommended to tie it to VCC when possible.
4 GND power_in Ground reference for the power supply, which should be connected to system ground.
5 SI (I/O0) input Serial input that latches command, address and data on the rising edge of SCK and is ignored when the device is deselected; it becomes I/O0 in the Dual-Output Read commands.
6 SCK input Serial clock that controls the data flow, with input data latched on the rising edge and output data clocked out on the falling edge.
7 HOLD input Pauses serial communication without deselecting or resetting the device when asserted (with CS asserted and SCK low), is internally pulled high and may be left floating if unused.
8 VCC power_in Device power supply pin; operation at invalid VCC voltages may produce spurious results and should not be attempted, with the part specified for 2.3V to 3.6V.

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor Adesto Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.35 0.6 µA CS = VCC. All other inputs at 0V or VCC. 29
Deep Power-Down Current IDPD 7.5 15 µA CS = VCC. All other inputs at 0V or VCC 29
Standby Current ISB 25 40 µA CS = VCC. All other inputs at 0V or VCC 29
Active Current, Low Power Read (03h, 0Bh) Operation ICC1 6 11 mA f = 1MHz; IOUT = 0mA 29
Active Current, Low Power Read (03h, 0Bh) Operation ICC1 7 11 mA f = 20MHz; IOUT = 0mA 29
Active Current, Read Operation ICC2 7 11 mA f = 50MHz; IOUT = 0mA 29
Active Current, Read Operation ICC2 7 12 mA f = 85MHz; IOUT = 0mA 29
Active Current, Program Operation ICC3 12 16 mA CS = VCC 29
Active Current, Erase Operation ICC4 12 18 mA CS = VCC 29
Input Load Current ILI 1 µA All inputs at CMOS levels 29
Output Leakage Current ILO 1 µA All inputs at CMOS levels 29
Output Low Voltage VOL 0.4 V IOL = 100µA 30
Maximum Clock Frequency for All Operations fCLK 104 MHz Including 0Bh opcode 30
Maximum Clock Frequency for 03h Opcode (Read Array, Low Frequency) fRDLF 33 MHz 03h opcode 30
Maximum Clock Frequency for 3B Opcode fRDDO 50 MHz 3B opcode 30
Clock High Time tCLKH 4 ns 30
Clock Low Time tCLKL 4 ns 30
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 30
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns 30
Chip Select High Time tCSH 25 ns 30
Chip Select Low Setup Time (relative to Clock) tCSLS 5 ns 30
Chip Select Low Hold Time (relative to Clock) tCSLH 5 ns 30
Chip Select High Setup Time (relative to Clock) tCSHS 5 ns 30
Chip Select High Hold Time (relative to Clock) tCSHH 5 ns 31
Data In Setup Time tDS 2 ns 30
Data In Hold Time tDH 1 ns 30
Output Disable Time tDIS 6 ns Not 100% tested 31
Output Valid Time tV 6 ns 31
Output Hold Time tOH 0 ns 31
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 31
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 31
HOLD High Setup Time (relative to Clock) tHHS 5 ns 31
HOLD High Hold Time (relative to Clock) tHHH 5 ns 31
HOLD Low to Output High-Z tHLQZ 6 ns Not 100% tested 31
HOLD High to Output Low-Z tHHQX 6 ns Not 100% tested 31
Write Protect Setup Time tWPS 20 ns Only applicable when BPL = 1 31
Write Protect Hold Time tWPH 100 ns Only applicable when BPL = 1 31
Chip Select High to Deep Power-Down tEDPD 2 µs Not 100% tested 31
Chip Select High to Ultra Deep Power-Down tEUDPD 3 µs 31
Software Reset Time tSWRST 50 µs 31
Minimum Chip Select Low to Exit Ultra Deep Power-Down tCSLU 20 ns 32
Exit Ultra Deep Power-Down Time tXUDPD 70 µs 32
Chip Select High to Standby Mode tRDPD 8 µs Not 100% tested 32
Page Program Time 256 Bytes tPP 1.25 1.75 ms 256 Bytes 32
Byte Program Time tBP 8 µs 32
Page Erase Time 256 Bytes tPE 6 20 ms 256 Bytes 32
Block Erase Time 4 Kbytes tBLKE 35 50 ms 4 Kbytes 32
Block Erase Time 32 Kbytes tBLKE 250 350 ms 32 Kbytes 32
Chip Erase Time tCHPE 500 700 ms 32
OTP Security Register Program Time tOTPP 400 950 µs 32
Write Status Register Time tWRSR 20 40 ms 32
Minimum VCC to Chip Select Low Time tVCSL 70 µs 32
Power-up Device Delay Before Program or Erase Allowed tPUW 5 ms 32
Power-on Reset Voltage VPOR 1.6 2.2 V 32
Temperature under Bias -55 125 °C 29
Storage Temperature -65 150 °C 29
All Input Voltages (including NC Pins) with respect to Ground -0.6 4.1 V with respect to Ground 29
All Output Voltages with respect to Ground -0.6 V with respect to Ground 29
Operating Temperature (Case) Industrial -40 85 °C 29
VCC Power Supply VCC 2.3 3.6 V 29

CAD (KiCad official)

  • Symbol: AT25DN512C-SSHF-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25dn512c-sshf-t-etched.step / at25dn512c-sshf-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25dn512c-sshf-t.step / at25dn512c-sshf-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor Adesto Adesto Technologies datasheet (40 pp, sha256 da4a4645280babb4, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF