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AT25DN011-SSHF-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

AT25DN011-SSHF-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25DN011-SSHF-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select: asserting selects the device, deasserting deselects it into standby (not Deep Power-Down) and puts SO in high impedance, and a high-to-low transition is required to start an operation.
2 SO (I/O1) bidirectional Serial output that shifts data out on the falling edge of SCK, becomes I/O1 in Dual-Output Read, and is high-impedance whenever the device is deselected.
3 WP input Active-low write protect controlling hardware locking of protected sectors; internally pulled high and may be left floating if unused, though connecting it to VCC is recommended.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SI (I/O0) bidirectional Serial input for all command, address and data input, latched on the rising edge of SCK, and becomes output I/O0 in Dual-Output Read; ignored when the device is deselected.
6 SCK input Serial clock controlling data flow, with input latched on the rising edge and output on the SO pin clocked out on the falling edge.
7 HOLD input Active-low hold that pauses serial communication without deselecting the device (CS asserted and SCK low required to start a Hold); internally pulled high and may be left floating if unused, though connecting it to VCC is recommended.
8 VCC power_in Device power supply, 2.3V to 3.6V; operation at invalid VCC voltages may produce spurious results and should not be attempted.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under Bias -55 125 °C 30
Storage Temperature -65 150 °C 30
All Input Voltages (including NC pins) with respect to Ground -0.6 4.1 V 30
All Output Voltages with respect to Ground -0.6 V upper limit printed as VCC + 0.5V 30
Operating Temperature (Case) -40 85 °C Industrial 30
VCC Power Supply VCC 2.3 3.6 V 30
Ultra-Deep Power-Down Current IUDPD 0.35 0.6 µA CS = VCC. All other inputs at 0V or VCC 31
Deep Power-Down Current IDPD 7.5 15 µA CS = VCC. All other inputs at 0V or VCC 31
Standby Current ISB 25 40 µA CS = VCC. All other inputs at 0V or VCC 31
Active Current, Low Power Read (03h, 0Bh) ICC1 6 11 mA f = 1MHz; IOUT = 0mA 31
Active Current, Low Power Read (03h, 0Bh) ICC1 7 11 mA f = 20MHz; IOUT = 0mA 31
Active Current, Read Operation ICC2 7 11 mA f = 50MHz; IOUT = 0mA 31
Active Current, Read Operation ICC2 7 12 mA f = 85MHz; IOUT = 0mA 31
Active Current, Program Operation ICC3 12 16 mA CS = VCC 31
Active Current, Erase Operation ICC4 12 18 mA CS = VCC 31
Input Load Current ILI 1 µA All inputs at CMOS levels 31
Output Leakage Current ILO 1 µA All inputs at CMOS levels 31
Output Low Voltage VOL 0.4 V IOL = 100µA 31
Maximum Clock Frequency for All Operations (including 0Bh opcode) fCLK 104 MHz 31
Maximum Clock Frequency for 03h Opcode (Read Array, Low Frequency) fRDLF 33 MHz 31
Maximum Clock Frequency for 3B Opcode fRDDO 50 MHz 31
Clock High Time tCLKH 4 ns 32
Clock Low Time tCLKL 4 ns 32
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns Not 100% tested 32
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns Not 100% tested 32
Chip Select High Time tCSH 25 ns 32
Chip Select Low Setup Time (relative to Clock) tCSLS 5 ns 32
Chip Select Low Hold Time (relative to Clock) tCSLH 5 ns 32
Chip Select High Setup Time (relative to Clock) tCSHS 5 ns 32
Chip Select High Hold Time (relative to Clock) tCSHH 5 ns 32
Data In Setup Time tDS 2 ns 32
Data In Hold Time tDH 1 ns 32
Output Disable Time tDIS 6 ns Not 100% tested 32
Output Valid Time tV 6 ns 32
Output Hold Time tOH 0 ns 32
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 32
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 32
HOLD High Setup Time (relative to Clock) tHHS 5 ns 32
HOLD High Hold Time (relative to Clock) tHHH 5 ns 32
HOLD Low to Output High-Z tHLQZ 6 ns Not 100% tested 32
HOLD High to Output Low-Z tHHQX 6 ns Not 100% tested 32
Write Protect Setup Time tWPS 20 ns Not 100% tested; only for Write Status Register when BPL = 1 32
Write Protect Hold Time tWPH 100 ns Not 100% tested; only for Write Status Register when BPL = 1 32
Chip Select High to Deep Power-Down tEDPD 2 µs Not 100% tested 32
Chip Select High to Ultra Deep Power-Down tEUDPD 3 µs 32
Software Reset Time tSWRST 50 µs 32
Minimum Chip Select Low to Exit Ultra Deep Power-Down tCSLU 20 ns 32
Exit Ultra Deep Power-Down Time tXUDPD 70 µs 32
Chip Select High to Standby Mode tRDPD 8 µs Not 100% tested 32
Page Program Time tPP 1.25 1.75 ms 256 Bytes; max after 100,000 erase/program cycles 33
Byte Program Time tBP 8 µs 33
Page Erase Time tPE 6 20 ms 256 Bytes 33
Block Erase Time tBLKE 35 50 ms 4 Kbytes; max after 100,000 erase/program cycles 33
Block Erase Time tBLKE 250 350 ms 32 Kbytes; max after 100,000 erase/program cycles 33
Chip Erase Time tCHPE 1000 1400 ms max after 100,000 erase/program cycles; not 100% tested 33
OTP Security Register Program Time tOTPP 400 950 µs max after 100,000 erase/program cycles 33
Write Status Register Time tWRSR 20 40 ms Not 100% tested 33
Minimum VCC to Chip Select Low Time tVCSL 70 µs 33
Power-up Device Delay Before Program or Erase Allowed tPUW 5 ms 33
Power-on Reset Voltage VPOR 1.6 2.2 V 33

CAD (KiCad official)

  • Symbol: AT25DN011-SSHF-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25dn011-sshf-t-etched.step / at25dn011-sshf-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25dn011-sshf-t.step / at25dn011-sshf-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (41 pp, sha256 bb22c59522339100, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF