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AT25512N-SH-B

Microchip Tech · EEPROM · SOIC-8

AT25512N-SH-B from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select: the device is selected when CS is low, and when it is high SI is not accepted and SO remains in high impedance.
2 SO tri_state Serial Data Output: shifts data out on SO during reads, and SO stays in a high-impedance state when the device is not selected or after an invalid opcode.
3 WP input Write Protect: when held low with WPEN set to one, all status register write operations are inhibited, and the WP function is blocked when WPEN is zero.
4 GND power_in Ground reference for the device.
5 SI input Serial Data Input: data and opcodes are received on SI, and SI is ignored while the device is not selected or while SO is in high impedance during Hold.
6 SCK input Serial Clock: always an input that clocks serial data on SI and SO, with the device operating as a slave.
7 HOLD input Suspend Serial Input: when CS is low and SCK is low, driving HOLD low pauses serial communication without resetting the sequence, and driving it high while SCK is low resumes it.
8 VCC power_in Power supply, specified from 1.8 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature -55 125 C 2
Storage Temperature -65 150 C 2
Voltage on any pin with respect to ground -1 7 V with respect to ground 2
Maximum Operating Voltage 6.25 V 2
DC Output Current 5 mA 2
Industrial operating temperature range TAI -40 85 C 4
Supply Voltage VCC1 1.8 5.5 V 4
Supply Voltage VCC2 2.7 5.5 V 4
Supply Voltage VCC3 4.5 5.5 V 4
Output Capacitance (SO) COUT 8 pF VOUT = 0V; TA = 25C, f = 1.0MHz, VCC = 5.0V 4
Input Capacitance (CS, SCK, SI, WP, HOLD) CIN 6 pF VIN = 0V; TA = 25C, f = 1.0MHz, VCC = 5.0V 4
Supply Current (read, 20MHz) ICC1 9 10 mA VCC = 5.0V at 20MHz, SO = Open, Read 4
Supply Current (read/write, 10MHz) ICC2 5 7 mA VCC = 5.0V at 10MHz, SO = Open, Read, Write 4
Supply Current (read/write, 1MHz) ICC3 2.2 3.5 mA VCC = 5.0V at 1MHz, SO = Open, Read, Write 4
Standby Current ISB1 0.2 3 μA VCC = 1.8V, CS = VCC 4
Standby Current ISB2 0.5 3 μA VCC = 2.7V, CS = VCC 4
Standby Current ISB3 2 5 μA VCC = 5.0V, CS = VCC 4
Input Leakage IIL -3 3 μA VIN = 0V to VCC 4
Output Leakage IOL -3 3 μA VIN = 0V to VCC, TAC = 0C to 70C 4
Input Low-voltage VIL -1 V 4
Output Low-voltage VOL1 0.4 V 3.6V ≤ VCC ≤ 5.5V, IOL = 3.0mA 4
Output Low-voltage VOL2 0.2 V 1.8V ≤ VCC ≤ 3.6V, IOL = 0.15mA 4
SCK Clock Frequency fSCK 0 20 MHz VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK Clock Frequency fSCK 0 10 MHz VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK Clock Frequency fSCK 0 5 MHz VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
Input Rise Time tRI 2 μs VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
Input Fall Time tFI 2 μs VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK High Time tWH 20 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK High Time tWH 40 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK High Time tWH 80 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK Low Time tWL 20 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK Low Time tWL 40 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
SCK Low Time tWL 80 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
CS High Time tCS 100 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
CS High Time tCS 200 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
CS Setup Time tCSS 100 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
CS Setup Time tCSS 200 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
CS Hold Time tCSH 100 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
CS Hold Time tCSH 200 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Setup Time tSU 5 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Setup Time tSU 10 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Setup Time tSU 20 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Hold Time tH 5 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Hold Time tH 10 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
Data In Hold Time tH 20 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Setup Time tHD 5 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Setup Time tHD 10 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Setup Time tHD 20 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Hold Time tCD 5 ns VCC 4.5V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Hold Time tCD 10 ns VCC 2.7V-5.5V, CL = 1 TTL Gate and 30pF 5
Hold Hold Time tCD 20 ns VCC 1.8V-5.5V, CL = 1 TTL Gate and 30pF 5

CAD (KiCad official)

  • Symbol: AT25512N-SH-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25512n-sh-b-etched.step / at25512n-sh-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25512n-sh-b.step / at25512n-sh-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (21 pp, sha256 b05a67d6b680295a, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF