component
AT24C512C-SSHM-T
Public Made by Adomby adom
Microchip EEPROM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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at24c512c-sshm-t: laser-etched CAD + chip hero (factory 2.0.0 backfill)
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AT24C512C-SSHM-T
Microchip · EEPROM · SOP-8
AT24C512C-SSHM-T from Microchip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input bit 0. Hardwire to VCC or GND to set one of up to 8 unique bus addresses; if left floating it is internally pulled to GND, but a defined connection (10 kOhm or less pull) is recommended due to capacitive coupling. |
| 2 | A1 | input | Device address input bit 1. Hardwire to VCC or GND to select the device address; internally pulled to GND if floating. Recommended external tie (<=10 kOhm) to a known state. |
| 3 | A2 | input | Device address input bit 2. Combined with A1/A0 to give up to 8 devices per I2C bus. Internally pulled to GND if floating; recommended external tie (<=10 kOhm). |
| 4 | GND | power_in | Device ground / 0 V reference. |
| 5 | SDA | bidirectional | I2C serial data. Bidirectional, open-drain output; requires an external pull-up resistor (typ 1.3 kOhm at 2.5-5V, 10 kOhm at 1.7V). Wire-ORable with other open-drain devices on the bus. |
| 6 | SCL | input | I2C serial clock input. Positive edges clock data into the device; negative edges clock data out. Supports up to 400 kHz at 1.7V and 1 MHz at 2.5-5.5V. |
| 7 | WP | input | Write Protect. Tie to GND for normal read/write operation; tie to VCC to inhibit all writes to the array (full-array protection). Internally pulled to GND if floating; recommended external tie (<=10 kOhm) to a known state. |
| 8 | VCC | power_in | Positive supply. 1.7-3.6V (VCC1) or 2.5-5.5V (VCC2) depending on device variant. Absolute max 6.25V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
AT24C512C-SSHM-TAT24C512C-SSHM-TXHM-TAT24C512C-SSHM-TXHMAT24C512C-SSHM-TMAHM-TAT24C512C-SSHM-TMAHMAT24C512C-SSHM-TCUHM-TAT24C512C-SSHM-TCUHM
CAD (KiCad official)
- Symbol:
AT24C512C-SSHM-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
at24c512c-sshm-t-etched.step/at24c512c-sshm-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at24c512c-sshm-t.step/at24c512c-sshm-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip datasheet (21 pp, sha256
9a744ba063c1f9ee, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AT24C512C-SSHM-T
**Microchip** · EEPROM · SOP-8
AT24C512C-SSHM-T from Microchip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input bit 0. Hardwire to VCC or GND to set one of up to 8 unique bus addresses; if left floating it is internally pulled to GND, but a defined connection (10 kOhm or less pull) is recommended due to capacitive coupling. |
| 2 | A1 | input | Device address input bit 1. Hardwire to VCC or GND to select the device address; internally pulled to GND if floating. Recommended external tie (<=10 kOhm) to a known state. |
| 3 | A2 | input | Device address input bit 2. Combined with A1/A0 to give up to 8 devices per I2C bus. Internally pulled to GND if floating; recommended external tie (<=10 kOhm). |
| 4 | GND | power_in | Device ground / 0 V reference. |
| 5 | SDA | bidirectional | I2C serial data. Bidirectional, open-drain output; requires an external pull-up resistor (typ 1.3 kOhm at 2.5-5V, 10 kOhm at 1.7V). Wire-ORable with other open-drain devices on the bus. |
| 6 | SCL | input | I2C serial clock input. Positive edges clock data into the device; negative edges clock data out. Supports up to 400 kHz at 1.7V and 1 MHz at 2.5-5.5V. |
| 7 | WP | input | Write Protect. Tie to GND for normal read/write operation; tie to VCC to inhibit all writes to the array (full-array protection). Internally pulled to GND if floating; recommended external tie (<=10 kOhm) to a known state. |
| 8 | VCC | power_in | Positive supply. 1.7-3.6V (VCC1) or 2.5-5.5V (VCC2) depending on device variant. Absolute max 6.25V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
## Ordering variants
- `AT24C512C-SSHM-T`
- `AT24C512C-SSHM-TXHM-T`
- `AT24C512C-SSHM-TXHM`
- `AT24C512C-SSHM-TMAHM-T`
- `AT24C512C-SSHM-TMAHM`
- `AT24C512C-SSHM-TCUHM-T`
- `AT24C512C-SSHM-TCUHM`
## CAD (KiCad official)
- Symbol: `AT24C512C-SSHM-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `at24c512c-sshm-t-etched.step` / `at24c512c-sshm-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at24c512c-sshm-t.step` / `at24c512c-sshm-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip datasheet](docs/at24c512c-sshm-t-datasheet.pdf) (21 pp, sha256 `9a744ba063c1f9ee`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/at24c512c-sshm-t-datasheet.pdf)