# AT24C256N

**HGSEMI** · EEPROM · DIP-8

AT24C256N from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input that is hardwired to VIH or VIL, and is read as VIL if left unconnected. |
| 2 | A1 | input | Device address input that is hardwired to VIH or VIL, and is read as VIL if left unconnected. |
| 3 | A2 | input | Device address input that is hardwired to VIH or VIL, and is read as VIL if left unconnected. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data line that is bi-directional with an open-drain output, so it can be wire-ORed and is typically pulled high by an external resistor. |
| 6 | SCL | input | Serial clock input where the rising edge latches data into the EEPROM and the falling edge clocks data out. |
| 7 | WP | input | Write protect input that blocks all programming when connected to VIH or VCC, allows programming when left unconnected or at VIL, and does not affect reads. |
| 8 | VCC | power_in | Supply voltage of 1.8V to 5.5V, with a decoupling capacitor of at least 10nF recommended. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Clock frequency, SCL | fSCL |  |  | 400 | kHz | VCC 1.8V column | 9 |
| Clock frequency, SCL | fSCL |  |  | 1000 | kHz | VCC 2.5-5.0V column | 9 |
| Noise suppression time | tI |  |  | 100 | ns | VCC 1.8V column | 9 |
| Noise suppression time | tI |  |  | 50 | ns | VCC 2.5-5.0V column | 9 |
| Clock pulse width low | tLOW | 1.3 |  |  | µs | VCC 1.8V column | 9 |
| Clock pulse width low | tLOW | 0.4 |  |  | µs | VCC 2.5-5.0V column | 9 |
| Clock pulse width high | tHIGH | 0.6 |  |  | µs | VCC 1.8V column | 9 |
| Clock pulse width high | tHIGH | 0.4 |  |  | µs | VCC 2.5-5.0V column | 9 |
| Clock low to data out valid | tAA |  |  | 0.9 | µs | VCC 1.8V column | 9 |
| Clock low to data out valid | tAA |  |  | 0.55 | µs | VCC 2.5-5.0V column | 9 |
| Time the bus must be free before a new transmission can start | tBUF | 1.3 |  |  | µs | VCC 1.8V column | 9 |
| Time the bus must be free before a new transmission can start | tBUF | 0.5 |  |  | µs | VCC 2.5-5.0V column | 9 |
| START hold time | tHD.STA | 0.6 |  |  | µs | VCC 1.8V column | 9 |
| START hold time | tHD.STA | 0.25 |  |  | µs | VCC 2.5-5.0V column | 9 |
| START set-up time | tSU.STA | 0.6 |  |  | µs | VCC 1.8V column | 9 |
| START set-up time | tSU.STA | 0.25 |  |  | µs | VCC 2.5-5.0V column | 9 |
| Data in hold time | tHD.DAT | 0 |  |  | µs | VCC 1.8V column | 9 |
| Data in set-up time | tSU.DAT | 100 |  |  | ns | VCC 1.8V column | 9 |
| Input rise time | tR |  |  | 0.3 | µs | VCC 1.8V column | 9 |
| Input fall time | tF |  |  | 300 | ns | VCC 1.8V column | 9 |
| Input fall time | tF |  |  | 100 | ns | VCC 2.5-5.0V column | 9 |
| STOP set-up time | tSU.STO | 0.6 |  |  | µs | VCC 1.8V column | 9 |
| STOP set-up time | tSU.STO | 0.25 |  |  | µs | VCC 2.5-5.0V column | 9 |
| Data out hold time | tDH | 50 |  |  | ns | VCC 1.8V column | 9 |
| VCC slew rate at power up | tPWR,R | 0.1 |  | 50 | V/ms | VCC 1.8V column | 9 |
| Time required after VCC is stable before the device can accept commands | tPUP | 100 |  |  | µs | VCC 1.8V column | 9 |
| Minimum time at VCC=0V between power cycles | tPOFF | 500 |  |  | ms | VCC 1.8V column | 9 |
| Write cycle time | tWR |  |  | 5 | ms | VCC 1.8V column | 9 |
| Endurance |  | 1e+06 |  |  | write cycles | 25℃, Page Mode, 3.3V | 9 |
| 24C256 supply | VCC1 | 1.8 |  | 5.5 | V |  | 10 |
| Supply read current | ICC1 |  | 0.4 | 1 | mA | VCC @ 5.0V SCL = 100 kHz | 10 |
| Supply write current | ICC2 |  | 2 | 3 | mA | VCC @ 5.0V SCL = 100 kHz | 10 |
| Supply current | ISB1 |  |  | 1 | µA | VCC @ 1.8V, VIN = VCC or VSS | 10 |
| Input leakage current | IIL |  |  | 3 | µA | VIN = VCC or VSS | 10 |
| Output leakage current | ILO |  |  | 3 | µA | VIN = VCC or VSS | 10 |
| Input low level | VIL | -0.6 |  |  | V |  | 10 |
| Output low level | VOL2 |  |  | 0.4 | V | VCC @ 3.0V, IOL = 2.1 mA | 10 |
| Industrial operating temperature |  | -40 |  | 85 | ℃ |  | 2 |
| Storage temperature |  | -50 |  | 125 | ℃ |  | 2 |
| Maximum voltage |  |  |  | 8 | V |  | 2 |
| Input voltage on any pin relative to ground |  | -0.3 |  |  | V | relative to ground | 2 |
| ESD protection on all pins |  | 2000 |  |  | V | all pins | 2 |

## CAD (KiCad official)

- Symbol: `AT24C256N`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `at24c256n-etched.step` / `at24c256n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at24c256n.step` / `at24c256n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912606908461056) (11 pp, sha256 `d7220784e4d64aba`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at24c256n-datasheet.pdf)