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AT24C1024BN-SH-T

Tudi · EEPROM · SOP-8

AT24C1024BN-SH-T from Tudi, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin, not internally used per the 8-lead SOP pinout drawing.
2 A1 input Device address input that is hard wired; up to four 1M devices can share a bus and the pin is biased to logic low internally if left floating.
3 A2 input Device address input that is hard wired; up to four 1M devices can share a bus and the pin is biased to logic low internally if left floating.
4 GND power_in Ground.
5 SDA bidirectional Bidirectional serial data pin, open-drain driven and may be wire-ORed with other open-drain or open-collector devices.
6 SCL input Serial clock input that positive-edge clocks data into the EEPROM and negative-edge clocks data out.
7 WP input Write protect input; normal read/write operation when connected to GND, and write protection of the full array enabled when connected to VCC.
8 VCC power_in Power supply, 1.7V to 5.5V.

Key specifications

Parameter Value
Manufacturer Tudi
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC1 1.7 5.5 V 10
Input Low Level VIL1 -0.3 V VCC=1.7V to 5.5V 10
Output Low Level VOL1 0.2 V VCC=1.7V, IOL=2.1mA 10
Output Low Level VOL2 0.4 V VCC=5.0V, IOL=3.0mA 10
Supply Current READ ICC1 0.26 0.5 mA READ at 400KHZ, VCC=5.0V 10
Supply Current WRITE ICC2 0.28 0.5 mA WRITE at 400KHZ, VCC=5.0V 10
Supply Current standby ISB1 0.03 0.5 μA VCC=5.0V, VIN=VCC or VSS 10
Input Leakage Current IL1 0.1 1 μA VIN=VCC or VSS 10
Output Leakage Current ILO 0.05 1 μA VOUT=VCC or VSS 10
Input Capacitance (A1,A2,SCL) CIN 6 pF VIN=0V 10
Input/Output Capacitance (SDA) CI/O 8 pF =0V 10
Clock Frequency, SCL (1.7V≤VCC<2.5V column) fSCL 400 kHZ 1.7V≤VCC<2.5V; CL=100 pF 11
Clock Frequency, SCL (2.5V≤VCC<5.5V column) fSCL 1000 kHZ 2.5V≤VCC<5.5V; CL=100 pF 11
Clock Pulse Width Low (1.7V column) tLOW 1.3 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Clock Pulse Width Low (2.5V column) tLOW 0.5 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Clock Pulse Width High (1.7V column) tHIGH 0.6 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Clock Pulse Width High (2.5V column) tHIGH 0.26 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Noise Suppression Time (1.7V column) tI 50 ns 1.7V≤VCC<2.5V; CL=100 pF 11
Noise Suppression Time (2.5V column) tI 50 ns 2.5V≤VCC<5.5V; CL=100 pF 11
Clock Low to Data Out Valid (1.7V column) tAA 0.9 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Clock Low to Data Out Valid (2.5V column) tAA 0.45 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Bus free time before new transmission (1.7V column) tBUF 1.3 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Bus free time before new transmission (2.5V column) tBUF 0.5 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Start Hold Time (1.7V column) tHD:STA 0.6 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Start Hold Time (2.5V column) tHD:STA 0.25 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Start Setup Time (1.7V column) tSU:STA 0.6 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Start Setup Time (2.5V column) tSU:STA 0.25 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Data In Hold Time (1.7V column) tHD:DAT 0 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Data In Hold Time (2.5V column) tHD:DAT 0 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Data in Setup Time (1.7V column) tSU:DAT 100 ns 1.7V≤VCC<2.5V; CL=100 pF 11
Data in Setup Time (2.5V column) tSU:DAT 100 ns 2.5V≤VCC<5.5V; CL=100 pF 11
Input Rise Time (1.7V column) tR 0.3 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Input Rise Time (2.5V column) tR 0.12 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Input Fall Time (1.7V column) tF 0.3 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Input Fall Time (2.5V column) tF 0.12 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Stop Setup Time (1.7V column) tSu:STO 0.6 μs 1.7V≤VCC<2.5V; CL=100 pF 11
Stop Setup Time (2.5V column) tSu:STO 0.25 μs 2.5V≤VCC<5.5V; CL=100 pF 11
Data Out Hold Time (1.7V column) tDH 50 ns 1.7V≤VCC<2.5V; CL=100 pF 11
Data Out Hold Time (2.5V column) tDH 50 ns 2.5V≤VCC<5.5V; CL=100 pF 11
Write Cycle Time (1.7V column) tWR 3.5 5 ms 1.7V≤VCC<2.5V 11
Write Cycle Time (2.5V column) tWR 3.5 5 ms 2.5V≤VCC<5.5V 11
DC Supply Voltage -0.3 6.5 V 10
Storage Temperature -65 150 ℃ 10
Electrostatic pulse (Human Body model) 8000 V Human Body model 10
Operating ambient temperature (AT24C1024 grade) TA -40 85 ℃ AT24C1024 TA=-40℃ to +85℃ 10

CAD (KiCad official)

  • Symbol: AT24C1024BN-SH-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: at24c1024bn-sh-t-etched.step / at24c1024bn-sh-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at24c1024bn-sh-t.step / at24c1024bn-sh-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Tudi datasheet (17 pp, sha256 111c342e808a843a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF