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AT24C04N

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by adom

HGSEMI EEPROM, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT24C04N

HGSEMI · EEPROM · DIP-8

AT24C04N from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input; unused (no connect, may be tied to ground) on the AT24C04.
2 A1 input Device address input used for hard-wire addressing on the AT24C04, where up to four 4K devices share a bus with A2.
3 A2 input Device address input used for hard-wire addressing on the AT24C04, where up to four 4K devices share a bus with A1.
4 GND power_in Ground.
5 SDA bidirectional Bidirectional open-drain serial data pin that may be wire-ORed with other open-drain or open-collector devices.
6 SCL input Serial clock input; positive edge clocks data into the EEPROM and negative edge clocks data out.
7 WP input Write protect: connected to GND allows normal read/write, connected to VCC write-protects the full 4K array.
8 VCC power_in Power supply, 1.7V to 5.5V (absolute maximum 6.5V).

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage -0.3 6.5 V 9
Operating Ambient Temperature -40 85 °C 9
Storage Temperature -65 150 °C 9
Lead Temperature (Soldering, 10 seconds) 260 °C Soldering, 10 seconds 9
Supply Voltage Vcc 1.7 5.5 V 9
Input Low Level VIL -0.6 V 9
Supply Current Read Icc1 0.4 1 mA Vcc=5.0V Read @100KHz 9
Supply Current Write Icc2 2 3 mA Vcc=5.0V Write @100KHz 9
Standby Current ISB 2 uA Vin=Vcc or GND 9
Input Leakage Current ILI 3 uA Vin=Vcc or GND 9
Output Leakage Current ILO 0.05 3 uA Vout=Vcc or GND 9
Output Low Level VOL3 0.4 V Vcc=5.0V IOL=3.0mA 9
Output Low Level VOL1 0.2 V Vcc=1.8V IOL=0.15mA 9
Input/Output Capacitance (SDA) CI/O 8 pF VI/O = 0V 9
Input Capacitance (A0, A1, A2, SCL) CIN 6 pF VIN = 0V 9
Clock Frequency, SCL (1.8-volt) fSCL 400 KHz 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Frequency, SCL (5.0-volt) fSCL 1000 KHz 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Pulse Width Low (1.8-volt) tLOW 1.2 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Pulse Width Low (5.0-volt) tLOW 0.6 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Pulse Width High (1.8-volt) tHIGH 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Pulse Width High (5.0-volt) tHIGH 0.4 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Noise Suppression Time (1.8-volt) tI 50 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Noise Suppression Time (5.0-volt) tI 40 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Low to Data Out Valid (1.8-volt) tAA 0.05 0.9 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Clock Low to Data Out Valid (5.0-volt) tAA 0.05 0.55 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Bus free time before new transmission (1.8-volt) tBUF 1.2 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Bus free time before new transmission (5.0-volt) tBUF 0.5 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Start Hold Time (1.8-volt) tHD.STA 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Start Hold Time (5.0-volt) tHD.STA 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Start Setup Time (1.8-volt) tSU.STA 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Start Setup Time (5.0-volt) tSU.STA 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Data In Hold Time (1.8-volt) tHD.DAT 0 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Data In Hold Time (5.0-volt) tHD.DAT 0 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Data In Setup Time (1.8-volt) tSU.DAT 100 ns 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Data In Setup Time (5.0-volt) tSU.DAT 100 ns 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Inputs Rise Time (1.8-volt) tR 0.3 us 1.8-volt column; note 1: characterized, not 100% tested 10
Inputs Rise Time (5.0-volt) tR 0.3 us 5.0-volt column; note 1: characterized, not 100% tested 10
Inputs Fall Time (1.8-volt) tF 300 ns 1.8-volt column; note 1: characterized, not 100% tested 10
Inputs Fall Time (5.0-volt) tF 100 ns 5.0-volt column; note 1: characterized, not 100% tested 10
Stop Setup Time (1.8-volt) tSU.STO 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Stop Setup Time (5.0-volt) tSU.STO 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Data Out Hold Time (1.8-volt) tDH 50 ns 1.8-volt column; CL = 1 TTL Gate and 100 pF 10
Data Out Hold Time (5.0-volt) tDH 50 ns 5.0-volt column; CL = 1 TTL Gate and 100 pF 10
Write Cycle Time (1.8-volt) tWR 5 ms 1.8-volt column 10
Write Cycle Time (5.0-volt) tWR 5 ms 5.0-volt column 10

CAD (KiCad official)

  • Symbol: AT24C04N
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: at24c04n-etched.step / at24c04n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at24c04n.step / at24c04n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (15 pp, sha256 157f59664dcbb8b3, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF