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AT24C04B-TH-T-TUDI

Public Made by Adom

by adom

Tudi EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT24C04B-TH-T-TUDI

Tudi · EEPROM · TSSOP-8

AT24C04B-TH-T-TUDI from Tudi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 unconnected Not used on the 4K device; the datasheet states the A0 pin is no connect for the AT24C04.
2 A1 input Hardwired device address input whose level must match the A1 device address bit on the 4K device.
3 A2 input Hardwired device address input whose level must match the A2 device address bit on the 4K device.
4 GND power_in Ground reference for the device.
5 SDA bidirectional Open-drain serial data pin for bidirectional transfer, normally pulled high by an external device and may be wire-ORed with other open-drain or open-collector devices.
6 SCL input Serial clock input that clocks data into the device on the positive edge and out of the device on the negative edge.
7 WP input Write protect input: connecting it to GND allows normal read/write operation, while connecting it to VCC enables write protection of the full array.
8 VCC power_in Power supply, specified from 1.7 V to 5.5 V over the recommended operating range.

Key specifications

Parameter Value
Manufacturer Tudi
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VCC, recommended operating range) VCC 1.7 5.5 V TA = -40℃ to +85℃ 10
Operating ambient temperature (recommended) TA -40 85 ℃ 10
DC supply voltage (absolute maximum) -0.3 6.5 V 10
Input / output voltage (absolute maximum, lower limit) -0.3 V referenced to GND 10
Input / output voltage (absolute maximum, upper limit) 0.3 V referenced to VCC (VCC+0.3V) 10
Operating ambient temperature (absolute maximum) -40 85 ℃ 10
Storage temperature (absolute maximum) -65 150 ℃ 10
Electrostatic pulse (Human Body model) 8000 V 10
Output low level, VCC=5.0V VOL2 0.4 V IOL=3.0mA 10
Output low level, VCC=1.7V VOL1 0.2 V IOL=0.15mA 10
Input high level (lower limit, ×VCC) VIH1 0.7 ×VCC VCC=1.7V to 5.5V 10
Input high level (upper limit, over VCC) VIH1 0.3 V over VCC VCC=1.7V to 5.5V 10
Input low level (lower limit) VIL1 -0.3 V VCC=1.7V to 5.5V 10
Input low level (upper limit, ×VCC) VIL1 0.3 ×VCC VCC=1.7V to 5.5V 10
Output leakage current ILO 0.05 1 µA VOUT=VCC or VSS 10
Input leakage current ILI 0.1 1 µA VIN=VCC or VSS 10
Standby supply current ISB1 0.03 0.5 µA VCC=5.0V 10
Supply current, WRITE ICC2 0.28 0.5 mA VCC=5.0V; WRITE at 400KHZ 10
Supply current, READ ICC1 0.14 0.3 mA VCC=5.0V; READ at 400KHZ 10
Supply voltage (write operation range) VCC2 2.5 5.5 V 10
Supply voltage (read operation range) VCC1 1.7 5.5 V 10
Input capacitance (A0, A1, A2, SCL) CIN 6 pF VIN=0V 10
Input/output capacitance (SDA) CI/O 8 pF VI/O=0V 10
Clock frequency, SCL (VCC 1.7V to <2.5V) fSCL 400 KHZ 1.7V≤VCC<2.5V 11
Clock frequency, SCL (VCC 2.5V to <5.5V) fSCL 1000 KHZ 2.5V≤VCC<5.5V 11
Write cycle time (VCC 1.7V to <2.5V) tWR 1.9 3 ms 1.7V≤VCC<2.5V 11
Write cycle time (VCC 2.5V to <5.5V) tWR 1.9 3 ms 2.5V≤VCC<5.5V 11
Data out hold time (VCC 1.7V to <2.5V) tDH 50 ns 1.7V≤VCC<2.5V 11
Data out hold time (VCC 2.5V to <5.5V) tDH 50 ns 2.5V≤VCC<5.5V 11
Stop setup time (VCC 1.7V to <2.5V) tSU:STO 0.25 µs 1.7V≤VCC<2.5V 11
Stop setup time (VCC 2.5V to <5.5V) tSU:STO 0.25 µs 2.5V≤VCC<5.5V 11
Input fall time (VCC 1.7V to <2.5V) tF 0.3 µs 1.7V≤VCC<2.5V 11
Input fall time (VCC 2.5V to <5.5V) tF 0.3 µs 2.5V≤VCC<5.5V 11
Input rise time (VCC 1.7V to <2.5V) tR 0.3 µs 1.7V≤VCC<2.5V 11
Input rise time (VCC 2.5V to <5.5V) tR 0.3 µs 2.5V≤VCC<5.5V 11
Data in setup time (VCC 1.7V to <2.5V) tSU:DAT 100 ns 1.7V≤VCC<2.5V 11
Data in setup time (VCC 2.5V to <5.5V) tSU:DAT 100 ns 2.5V≤VCC<5.5V 11
Data in hold time (VCC 1.7V to <2.5V) tHD:DAT 0 µs 1.7V≤VCC<2.5V 11
Data in hold time (VCC 2.5V to <5.5V) tHD:DAT 0 µs 2.5V≤VCC<5.5V 11
Start setup time (VCC 1.7V to <2.5V) SU:DAT 0.25 µs 1.7V≤VCC<2.5V 11
Start setup time (VCC 2.5V to <5.5V) SU:DAT 0.25 µs 2.5V≤VCC<5.5V 11
Start hold time (VCC 1.7V to <2.5V) tHD:STA 0.25 µs 1.7V≤VCC<2.5V 11
Start hold time (VCC 2.5V to <5.5V) tHD:STA 0.25 µs 2.5V≤VCC<5.5V 11
Bus free time before new transmission (VCC 1.7V to <2.5V) tBUF 0.5 µs 1.7V≤VCC<2.5V 11
Bus free time before new transmission (VCC 2.5V to <5.5V) tBUF 0.5 µs 2.5V≤VCC<5.5V 11
Clock low to data out valid (VCC 1.7V to <2.5V) tAA 0.1 0.55 µs 1.7V≤VCC<2.5V 11
Clock low to data out valid (VCC 2.5V to <5.5V) tAA 0.1 0.55 µs 2.5V≤VCC<5.5V 11
Noise suppression time (VCC 1.7V to <2.5V) tI 50 ns 1.7V≤VCC<2.5V 11
Noise suppression time (VCC 2.5V to <5.5V) tI 50 ns 2.5V≤VCC<5.5V 11
Clock pulse width high (VCC 1.7V to <2.5V) tHIGH 0.4 µs 1.7V≤VCC<2.5V 11
Clock pulse width high (VCC 2.5V to <5.5V) tHIGH 0.4 µs 2.5V≤VCC<5.5V 11
Clock pulse width low (VCC 1.7V to <2.5V) tLOW 0.6 µs 1.7V≤VCC<2.5V 11
Clock pulse width low (VCC 2.5V to <5.5V) tLOW 0.6 µs 2.5V≤VCC<5.5V 11

CAD (KiCad official)

  • Symbol: AT24C04B-TH-T-TUDI
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: at24c04b-th-t-tudi-etched.step / at24c04b-th-t-tudi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at24c04b-th-t-tudi.step / at24c04b-th-t-tudi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Tudi datasheet (18 pp, sha256 4c16636c4866f117, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF