component

AT24C02CDRG

Public Made by Adom

by adom

HANSCHIP semiconductor EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat24c02cdrgfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers at24c02cdrg: viewers · Ray 4d ago
at24c02cdrg-etched.glb Publish 0.1.0 · Ray 4d ago
at24c02cdrg-etched.step at24c02cdrg: factory component page (tier=lcsc) · Ray 4d ago
at24c02cdrg-hero.glb at24c02cdrg: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
at24c02cdrg-hero.overlay.json Publish 0.1.0 · Ray 4d ago
at24c02cdrg.glb Publish 0.1.0 · Ray 4d ago
at24c02cdrg.kicad_mod Publish 0.1.0 · Ray 4d ago
at24c02cdrg.kicad_sym Publish 0.1.0 · Ray 4d ago
at24c02cdrg.lbr Publish 0.1.0 · Ray 4d ago
at24c02cdrg.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago

AT24C02CDRG

HANSCHIP semiconductor · EEPROM · SOP-8

AT24C02CDRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E0 input Device address input that can be tied to VCC or GND in any combination (up to eight devices on a bus); internally pulled down to GND if left floating.
2 E1 input Device address input that can be tied to VCC or GND in any combination (up to eight devices on a bus); internally pulled down to GND if left floating.
3 E2 input Device address input that can be tied to VCC or GND in any combination (up to eight devices on a bus); internally pulled down to GND if left floating.
4 GND power_in Ground reference for the power supply, to be connected to system ground.
5 SDA bidirectional Open-drain bidirectional serial data pin used to transfer data to and from the device.
6 SCL input Serial clock input that controls data flow; input data is latched on the rising edge and output data is clocked out on the falling edge of SCL.
7 WP input Write protect input: connected to VCC the whole memory array is write-protected (read-only), connected to GND writes are enabled, and internally pulled down to GND if floating.
8 VCC power_in Device power supply, 1.7V to 5.5V; operation at invalid VCC voltages may produce spurious results.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature with power applied -55 130 °C 20
Storage temperature TSTG -65 150 °C 20
Supply voltage VCC -0.5 6 V 20
Voltage on input pins VIN -0.5 6 V 20
Electrostatic pulse (human body model) VESD 5000 V Human body model 20
Lead temperature (soldering) TL 245 °C Soldering, 10 seconds 20
Operating ambient temperature range TA -40 105 °C Operating range 20
Supply voltage VCC 1.7 5.5 V Operating range 20
Supply Current (Read) ICC1 0.1 mA VCC= 1.7V, Read at 1MHz 20
Supply Current (Read) ICC1 0.4 mA VCC= 5.5V, Read at 400 kHz 20
Supply Current (Read) ICC1 0.5 mA VCC= 5.5V, Read at 1MHz 20
Supply Current (Write) ICC2 0.2 mA VCC= 1.7V, Write at 400 kHz 20
Supply Current (Write) ICC2 0.5 mA VCC= 5.5V, Write at 400 kHz 20
Standby Current ISB 0.5 μA VCC = 1.7V, VIN = VCC or GND 20
Standby Current ISB 1 μA VCC = 5.5V, VIN = VCC or GND 20
Input Leakage Current ILI 1 μA VIN = VCC or GND 20
Output Leakage Current ILO 1 μA VOUT = VCC or GND 20
Input Low-Level Voltage (SDA, SCL) VIL -0.5 V Input Low-Level Voltage (SDA, SCL); max printed as 0.3*VCC (see next row) 20
Input Low-Level Voltage (SDA, SCL) VIL 0.3 ×VCC Input Low-Level Voltage (SDA, SCL); max printed as 0.3*VCC 20
Input High-Level Voltage (SDA, SCL) VIH 0.7 ×VCC Input High-Level Voltage (SDA, SCL); max printed as VCC+0.5 V 20
Low-Level Output Voltage VOL1 0.4 V VCC> 2V, IOL= 3mA 20
Low-Level Output Voltage VOL2 0.2 V VCC≤2V, IOL= 2mA 20
Clock Frequency, SCL (Fast Mode) fSCL 400 kHz Fast Mode, VCC = 1.7V to 5.5V 21
Clock Frequency, SCL (High Speed Mode) fSCL 1000 kHz High Speed Mode, VCC = 1.7V to 5.5V 21
Clock Pulse Width Low tLOW 1300 ns Fast Mode, VCC = 1.7V to 5.5V 21
Clock Pulse Width Low tLOW 600 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Clock Pulse Width High tHIGH 600 ns Fast Mode, VCC = 1.7V to 5.5V 21
Clock Pulse Width High tHIGH 260 ns High Speed Mode, VCC = 1.7V to 5.5V 21
SDA Rise Time tR 300 ns Fast Mode, VCC = 1.7V to 5.5V; ensured by characterization only 21
SDA(Out) Fall Time tF 300 ns Fast Mode, VCC = 1.7V to 5.5V; ensured by characterization only 21
SDA(Out) Fall Time tF 100 ns High Speed Mode, VCC = 1.7V to 5.5V; ensured by characterization only 21
Start Hold Time tHD.STA 600 ns Fast Mode, VCC = 1.7V to 5.5V 21
Start Hold Time tHD.STA 250 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Start Setup Time tSU.STA 600 ns Fast Mode, VCC = 1.7V to 5.5V 21
Start Setup Time tSU.STA 250 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Stop Setup Time tSU.STO 600 ns Fast Mode, VCC = 1.7V to 5.5V 21
Stop Setup Time tSU.STO 250 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Bus Free Time between Stop and Next Start tBUF 1300 ns Fast Mode, VCC = 1.7V to 5.5V 21
Bus Free Time between Stop and Next Start tBUF 500 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Data In Hold Time tHD.DI 0 ns Fast Mode, VCC = 1.7V to 5.5V 21
Data In Setup Time tSU.DAT 100 ns Fast Mode, VCC = 1.7V to 5.5V 21
Data In Setup Time tSU.DAT 50 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Data Out Hold Time tHD.DAT 50 ns Fast Mode, VCC = 1.7V to 5.5V 21
SCL Low to Data Out Valid tAA 100 900 ns Fast Mode, VCC = 1.7V to 5.5V 21
SCL Low to Data Out Valid tAA 50 500 ns High Speed Mode, VCC = 1.7V to 5.5V 21
WP Pin Setup Time tSU.WP 1200 ns Fast Mode, VCC = 1.7V to 5.5V 21
WP Pin Setup Time tSU.WP 600 ns High Speed Mode, VCC = 1.7V to 5.5V 21
WP Pin Hold Time tHD.WP 1200 ns Fast Mode, VCC = 1.7V to 5.5V 21
WP Pin Hold Time tHD.WP 600 ns High Speed Mode, VCC = 1.7V to 5.5V 21
Write Cycle Time tWR 5 ms Fast Mode, VCC = 1.7V to 5.5V 21
Noise Suppression Time tI 50 ns Fast Mode, VCC = 1.7V to 5.5V 21
Input/output Capacitance (SDA) CI/O 8 pF VI/O = 0V; TA = +25°C, fC = 1MHz, VCC = 1.7V to 5.5V 22
Input Capacitance (other Pins) CIN 6 pF VIN = 0V; TA = +25°C, fC = 1MHz, VCC = 1.7V to 5.5V 22
Data Retention DR 200 year TA = +25°C 22

CAD (KiCad official)

  • Symbol: AT24C02CDRG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: at24c02cdrg-etched.step / at24c02cdrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at24c02cdrg.step / at24c02cdrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (27 pp, sha256 30146010ee8ac6eb, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF