component
ASDM4100S-R
Public Made by Adomby adom
ASDsemi MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ASDM4100S-R
ASDsemi · MOSFETs · SOP-8
ASDM4100S-R from ASDsemi, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of Q1 (N-channel, 100 V, 5 A) MOSFET. |
| 2 | G1 | input | Gate of Q1 (N-channel) MOSFET, VGS rated ±20 V. |
| 3 | S2 | passive | Source of Q2 (P-channel, -100 V, -4 A) MOSFET. |
| 4 | G2 | input | Gate of Q2 (P-channel) MOSFET, VGS rated ±20 V. |
| 5 | D2 | passive | Drain of Q2 (P-channel, VDSS -100 V), internally tied to pin 6. |
| 6 | D2 | passive | Drain of Q2 (P-channel, VDSS -100 V), internally tied to pin 5. |
| 7 | D1 | passive | Drain of Q1 (N-channel, VDSS 100 V), internally tied to pin 8. |
| 8 | D1 | passive | Drain of Q1 (N-channel, VDSS 100 V), internally tied to pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ASDsemi |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (N-ch) | VDSS | 100 | V | 1 | |||
| Drain-Source Voltage (P-ch) | VDSS | -100 | V | 1 | |||
| Gate-Source Voltage (N-ch) | VGSS | -20 | 20 | V | 1 | ||
| Gate-Source Voltage (P-ch) | VGSS | -20 | 20 | V | 1 | ||
| Drain Current - Continuous (N-ch) | ID | 5 | A | Note 1a | 1 | ||
| Drain Current - Continuous (P-ch) | ID | -4 | A | Note 1a | 1 | ||
| Drain Current - Pulsed (N-ch) | ID | 20 | A | Pulsed | 1 | ||
| Drain Current - Pulsed (P-ch) | ID | -20 | A | Pulsed | 1 | ||
| Power Dissipation for Single Operation | PD | 1.6 | W | Note 1a | 1 | ||
| Power Dissipation for Single Operation | PD | 1 | W | Note 1b | 1 | ||
| Power Dissipation for Single Operation | PD | 0.9 | W | Note 1c | 1 | ||
| Operating and Storage Junction Temperature Range | TJ, TSTG | -55 | 150 | °C | 1 | ||
| Drain-Source Breakdown Voltage (N-ch) | BVDSS | 100 | V | VGS = 0 V, ID = 250 μA | 2 | ||
| Drain-Source Breakdown Voltage (P-ch) | BVDSS | -100 | V | VGS = 0 V, ID = -250 μA | 2 | ||
| Zero Gate Voltage Drain Current (N-ch) | IDSS | 1 | μA | VDS = 24 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (P-ch) | IDSS | -1 | μA | VDS = -24 V, VGS = 0 V | 2 | ||
| Gate-Body Leakage, Forward | IGSSF | 100 | nA | VGS = 20 V, VDS = 0 V | 2 | ||
| Gate-Body Leakage, Reverse | IGSSR | -100 | nA | VGS = -20 V, VDS = 0 V | 2 | ||
| Gate Threshold Voltage (N-ch) | VGS(th) | 1 | 1.6 | 3 | V | VDS = VGS, ID = 250 μA | 2 |
| Thermal Resistance, Junction-to-Ambient | RθJA | 78 | °C/W | Note 1a | 1 | ||
| Thermal Resistance, Junction-to-Case | RθJC | 40 | °C/W | Note 1 | 1 |
CAD (KiCad official)
- Symbol:
ASDM4100S-R - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
asdm4100s-r-etched.step/asdm4100s-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);asdm4100s-r.step/asdm4100s-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ASDsemi datasheet (9 pp, sha256
fe6e1dae3306ec62, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).