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ASDM20P09ZB-R

Ascend · MOSFETs · SOT-23-3

ASDM20P09ZB-R from Ascend, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; controls the P-channel MOSFET, with a gate-source voltage limit of ±12 V and a threshold of -0.4 to -1.0 V at ID = -250 µA.
2 S passive Source; P-channel source terminal, with drain-source voltage rated to -20 V and continuous drain current of -9 A at TC = 25 °C.
3 D passive Drain; P-channel drain terminal, with VDSS of -20 V, pulsed drain current of -15 A and RDS(on) below 21 mΩ at VGS = -4.5 V.

Key specifications

Parameter Value
Manufacturer Ascend
Package SOT-23-3
Category Transistors
Pins 3

CAD (KiCad official)

  • Symbol: ASDM20P09ZB-R
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3 (KiCad packages3D, STEP)
  • 3D model files: asdm20p09zb-r-etched.step / asdm20p09zb-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); asdm20p09zb-r.step / asdm20p09zb-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Ascend datasheet (7 pp, sha256 5288919391a75624, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF