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ASD80R750E

ANHI · MOSFETs · TO-252

ASD80R750E from ANHI, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate control pin of the N-channel MOSFET; VGS is rated at ±30 V static with threshold Vth of 2.8 to 4.2 V.
2 Drain passive Drain pin, also connected to the tab; VDS breakdown is 800 V min and continuous drain current is 8.5 A at TC=25°C.
3 Source passive Source pin of the N-channel MOSFET, connected to the body diode anode and the return path for drain current.

Key specifications

Parameter Value
Manufacturer ANHI
Package TO-252
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source breakdown voltage V(BR)DSS 800 V VGS=0V, ID=250uA 4
Gate threshold voltage V(GS)th 2.8 4.2 V VDS=VGS, ID=250uA 4
Zero gate voltage drain current IDSS 1 uA VDS=800V, VGS=0V, Tj=25°C 4
Gate-source leakage current IGSS 100 nA VGS=30V, VDS=0V 4
Drain-source on-state resistance RDS(on) 620 750 mΩ VGS=10V, ID=6A, Tj=25°C 4
Continuous drain current ID 8.5 A TC=25°C 2
Pulsed drain current ID,pulse 35 A TC=25°C 2
Avalanche energy, single pulse EAS 88 mJ Tc=25℃,VDD=50V, Iav=4.2A, L=10mH, RG=25Ω 2
Avalanche current, single pulse IAR 4.2 A Tc=25℃,VDD=50V, L=10mH, RG=25Ω 2
Gate source voltage (static) VGS -30 30 V static; 2
Power dissipation (TO252&263) Ptot 150 W TC=25°C 2
Storage temperature Tstg -55 150 °C 2
Operating junction temperature Tj -55 150 °C 2
Soldering temperature TL 260 °C Distance of 1.6mm from case for 10s 2
Reverse diode dv/dt dv/dt 4 V/ns VDS=0...400V, ISD<=8A, Tj=25°C 2
Thermal resistance, junction-case (TO252&263) RthJC 1.1 °C/W 3
Thermal resistance, junction-ambient (TO252&263) RthJA 62 °C/W device on PCB, minimal footprint 3
Gate resistance (Intrinsic) RG 25 Ω f=1MHz, open drain 4
Input capacitance Ciss 850.8 pF VGS=0V, VDS=100V, f=1MHz 4
Output capacitance Coss 34.4 pF VGS=0V, VDS=100V, f=1MHz 4
Reverse transfer capacitance Crss 0.92 pF VGS=0V, VDS=100V, f=1MHz 4
Turn-on delay time td(on) 40.6 ns VDD=400V,VGS=10V,ID=4.1A, RG=50Ω 4
Rise time tr 34.8 ns VDD=400V,VGS=10V,ID=4.1A, RG=50Ω 4
Turn-off delay time td(off) 128 ns VDD=400V,VGS=10V,ID=4.1A, RG=50Ω 4
Fall time tf 31 ns VDD=400V,VGS=10V,ID=4.1A, RG=50Ω 4
Gate to source charge Qgs 5 nC VDD=400V, ID=4.1A, VGS=0 to 10V 4
Gate to drain charge Qgd 6.6 nC VDD=400V, ID=4.1A, VGS=0 to 10V 4
Gate charge total Qg 18.5 nC VDD=400V, ID=4.1A, VGS=0 to 10V 4
Diode forward voltage VSD 0.75 V VGS=0V, IF=1A, Tj=25°C 5
Reverse recovery time trr 266.5 ns VR=400V, IF=4.1A, diF/dt=100A/µs 5
Reverse recovery charge Qrr 2.2 uC VR=400V, IF=4.1A, diF/dt=100A/µs 5
Peak reverse recovery current Irrm 14 A VR=400V, IF=4.1A, diF/dt=100A/µs 5

CAD (KiCad official)

  • Symbol: ASD80R750E
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: asd80r750e-etched.step / asd80r750e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); asd80r750e.step / asd80r750e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ANHI datasheet (12 pp, sha256 17e7a6e1602f4ec1, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF