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AS5048A-HTSP-500

Advanced Monolithic Systems · Angle, Linear Position Sensors · TSSOP-14

AS5048A-HTSP-500 from Advanced Monolithic Systems, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CSn	input	SPI chip select, active low, digital input with Schmitt trigger.
2	CLK	input	SPI clock input.
3	MISO	bidirectional	SPI master in/slave out, digital I/O with Schmitt trigger in the input path.
4	MOSI	input	SPI master out/slave in, digital input with Schmitt trigger.
5	TEST	passive	Analog I/O test pin that should be connected to GND.
6	TEST	unconnected	Analog I/O test pin that should be left open during normal operation.
7	TEST	unconnected	Analog I/O test pin that should be left open during normal operation.
8	TEST	unconnected	Analog I/O test pin that should be left open during normal operation.
9	TEST	unconnected	Analog I/O test pin that should be left open during normal operation.
10	TEST	unconnected	Analog I/O test pin that should be left open during normal operation.
11	VDD5V	power_in	Positive supply voltage, 3.0 to 5.5 V.
12	VDD3V	power_out	3.3V regulator output internally regulated from VDD; connect to VDD for 3V supply, and a 10μF capacitor to GND is required in 5V operation mode.
13	GND	power_in	Negative supply voltage (GND).
14	PWM	output	Digital push-pull Pulse Width Modulation output.

Key specifications

Parameter	Value
Manufacturer	Advanced Monolithic Systems
Package	TSSOP-14
Category	Sensors
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC supply voltage at VDD pin	VDD5V	-0.3		7	V		6
DC voltage at VDD3V pin	VDD3V	-0.3		5	V		6
DC voltage at GND pin	GND	-0.3		0.3	V		6
Input current (latchup immunity)	ISCR	-100		100	mA	Jedec 78	6
Electrostatic discharge	ESD	-2		2	kV	MIL 883 E method 3015	6
Total power dissipation	PT			150	mW	all supplies and outputs	6
Storage temperature	TSTRG	-55		150	°C		6
Package body temperature	TBODY			260	°C	IPC/JEDEC J-STD-020	6
Relative humidity non-condensing	RHNC	5		85	%		6
Positive supply voltage	VDD5V	4.5		5.5	V	5V Operation via LDO	7
LDO output voltage	VDD3V	3		3.6	V	LDO output voltage	7
Positive core supply voltage	VDDCORE	3		3.6	V		7
Ambient temperature	TAMB	-40		150	°C	Only for 5V operation. T_amb_max for 3V is 125°C	7
Supply current	ISUP			15	mA		7
Input leakage current	ILEAK			1	μA		7
Capacitive load	CL			50	pF		7
Output current	IOUT			4	mA		7
Magnetic input field	Bz	30	50	70	mT	VDD5V = 5V, TAMB = -40 to 150°C	8
Output sampling rate	fsample	10.2	11.25	12.4	kHz	VDD5V = 5V, TAMB = -40 to 150°C	8
System propagation delay	tprop	90.7	100	110.2	μs	VDD5V = 5V, TAMB = -40 to 150°C	8
PWM frequency	fPWM	0.907	1	1.102	kHz	VDD5V = 5V, TAMB = -40 to 150°C	8
Non-linearity, optimum placement of the magnet	INLOPT	-0.8		0.8	deg	@25ºC	8
Non-linearity optimum placement over full temperature range	INL OPT+TEMP	-1		1	deg		8
Non-linearity at displacement of magnet and temperature	INL DIS+TEMP	-1.2		1.2	deg	Assuming N35H magnet (D=8mm, H=3mm) 500μm displacement in x and y z-distance @ 2000μm	8
Startup time	tstartup			10	ms		8
Output resolution	RES		14		Bit	VDD5V = 5V, TAMB = -40 to 150°C	8
Sensor output noise	Noise		0.06		deg	2.73LSB@14bit, rms value	8
Time between CSn falling edge and CLK rising edge	tL	350			ns		12
Serial clock period	TCLK	100			ns		12
Low period of serial clock	tCLKL	50			ns		12
High period of serial clock	tCLKH	50			ns		12
Time between last falling edge of CLK and rising edge of CSn	tH	50			ns		12
High time of CSn between two transmissions	TCSnH	350			ns		12
Data input valid to clock edge	tMOSI	20			ns		12
CLK edge to data output valid	tMISO			20	ns		12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	The lead finish from Pb-free leaded packages is matte tin	6

CAD (KiCad official)

Symbol: AS5048A-HTSP-500
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: as5048a-htsp-500-etched.step / as5048a-htsp-500-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); as5048a-htsp-500.step / as5048a-htsp-500.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Advanced Monolithic Systems datasheet (41 pp, sha256 fea8c4c785743e0f, retrieved 2026-10-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF