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AS5040-ASST

AMS · Signal Switches, Multiplexers, Decoders · SSOP-16-208mil

AS5040-ASST from AMS, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MagINCn	output	Magnet field magnitude increase indicator, active low, signals a reduced distance between magnet and device; open-drain digital output.
2	MagDECn	output	Magnet field magnitude decrease indicator, active low, signals an increased distance between device and magnet; open-drain digital output.
3	A_LSB_U	output	Mode 1.x quadrature A channel, Mode 2.x least significant bit (LSB), Mode 3.x U signal (phase 1) of the incremental interface.
4	B_Dir_V	output	Mode 1.x quadrature B channel (quarter period shift to channel A), Mode 2.x direction of rotation, Mode 3.x V signal (phase 2).
5	NC	unconnected	Must be left unconnected.
6	Index_W	output	Mode 1.x and 2.x index signal indicating the absolute zero position; Mode 3.x W signal (phase 3).
7	VSS	power_in	Negative supply voltage (GND).
8	Prog	input	OTP programming input and data input for daisy chain mode; internal pull-down resistor (~74 kΩ), may be connected to VSS if programming is not used.
9	DO	tri_state	Data output of the synchronous serial interface; tri-stated when CSn is high, which also terminates serial data transfer.
10	CLK	input	Clock input of the synchronous serial interface, Schmitt-trigger input.
11	CSn	input	Chip select, active low, Schmitt-trigger input with internal pull-up resistor (~50 kΩ); connect to VSS in incremental mode.
12	PWM_LSB	output	Pulse width modulated output of approx. 1 kHz (1 µs to 1024 µs over a full turn); provides the LSB in Mode 3.x.
13	NC	unconnected	Must be left unconnected.
14	NC	unconnected	Must be left unconnected.
15	VDD3V3	power_out	3 V regulator output of the internal LDO (see Figure 39 of the datasheet).
16	VDD5V	power_in	Positive supply voltage, 5 V.

Key specifications

Parameter	Value
Manufacturer	AMS
Package	SSOP-16-208mil
Category	Logic
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC supply voltage at pin VDD5V	VDD5V	-0.3		7	V		7
DC supply voltage at pin VDD3V3	VDD3V3	-0.3		5	V		7
Input pin voltage	Vin	-0.3			V		7
Input pin voltage (pins MagINCn, MagDECn, CLK, CSn)	Vin	-0.3		7.5	V	Pins MagINCn, MagDECn, CLK, CSn	7
Input current (latchup immunity)	Iscr	-100		100	mA	Norm: JEDEC 78	7
Electrostatic discharge	ESD	-2		2	kV	Norm: MIL 883 E method 3015	7
Storage temperature	Tstrg	-55		125	°C		7
Body temperature (lead-free package)	TBody			260	°C	t=20 to 40s, Norm: IPC/JEDEC J-Std-020C	7
Relative humidity (non condensing)	RHNC	5		85	%	Non condensing	7
Ambient temperature	Tamb	-40		125	°C		8
External supply voltage at pin VDD5V (5V operation)	VDD5V	4.5	5	5.5	V	5V operation	8
Internal regulator output voltage at pin VDD3V3 (5V operation)	VDD3V3	3	3.3	3.6	V	5V operation	8
External supply voltage at pin VDD5V (3.3V operation)	VDD5V	3	3.3	3.6	V	3.3V operation (pins VDD5V and VDD3V3 connected)	8
External supply voltage at pin VDD3V3 (3.3V operation)	VDD3V3	3	3.3	3.6	V	3.3V operation (pins VDD5V and VDD3V3 connected)	8
Supply current	Isupp		16	21	mA		8
Input leakage current	ILEAK	-1		1	μA	CLK only	8
Pull-up low level input current	IiL	-100		-30	μA	CSn only, VDD5V: 5.0V	8
High level input voltage (Prog)	VIH			5	V		9
Output current (MagINCn, MagDECn)	IO			4	mA	VDD5V: 4.5V	9
Output current (MagINCn, MagDECn)	IO			2	mA	VDD5V: 3V	9
Output current (A, B, Index, PWM)	IO			4	mA	VDD5V: 4.5V	10
Output current (A, B, Index, PWM)	IO			2	mA	VDD5V: 3V	10
Output current (DO)	IO			4	mA	VDD5V: 4.5V	10
Output current (DO)	IO			2	mA	VDD5V: 3V	10
Diameter	dmag	4		6	mm	Recommended magnet: Ø 6mm x 2.5mm	11
Magnetic input field amplitude	Bpk	45		75	mT	Vertical component of field on die surface, concentric circle radius 1.1mm	11
Magnetic offset	Boff	-10		10	mT	Constant magnetic stray field	11
Displacement radius	Disp			0.25	mm	Max. X-Y offset between defined IC package center and magnet axis	11
Displacement radius (chip center)	Disp			0.485	mm	Max. X-Y offset between chip center and magnet axis	11
Integral non-linearity (optimum)	INLopt	-0.5		0.5	deg	Optimum magnet placement, Tamb = 25 °C; max error vs best line fit	12
Integral non-linearity (optimum, temperature)	INLtemp	-0.9		0.9	deg	Optimum magnet placement, Tamb = -40°C to 125°C	12
Integral non-linearity	INL	-1.4		1.4	deg	Over displacement tolerance with 6mm diameter magnet, Tamb = -40°C to 125°C	12
Differential non-linearity	DNL	-0.176		0.176	deg	10bit, no missing codes	12
Power-on-reset threshold ON voltage	Von	1.37	2.2	2.9	V	DC supply voltage 3.3V (VDD3V3)	12
Power-on-reset threshold OFF voltage	Voff	1.08	1.9	2.6	V	DC supply voltage 3.3V (VDD3V3)	12
Sampling rate for absolute output	fS	9.9	10.42	10.94	kHz	Internal sampling rate, Tamb = 25°C	13
Sampling rate for absolute output	fS	9.38	10.42	11.46	kHz	Internal sampling rate, Tamb = -40°C to 125°C	13
CLK read-out frequency	CLK			1	MHz	Max. clock frequency to read out serial data	13
Data output valid	tDO valid	357		413	ns	Time between rising edge of CLK and data output valid	14
Read-out frequency	fCLK			1	MHz	Clock frequency to read out serial data	14
PWM frequency	fPWM	0.927	0.976	1.024	kHz	Signal period = 1025μs ±5% at Tamb = 25°C	15
PWM frequency	fPWM	0.878	0.976	1.074	kHz	Signal period = 1025μs ±10% at Tamb = -40°C to 125°C	15
Minimum pulse width	PWMIN	0.9	1	1.1	μs	Position 0d; angle 0 degree	15
Maximum pulse width	PWMAX	922	1024	1126	μs	Position 1023d; angle 359.65 degree	15
t PROG CLK pulse width	tPROG CLK	1.8	2	2.2	μs	During programming; 16 clock cycles	16
Programming voltage	VPROG	7.3	7.4	7.5	V		16
Programming voltage OFF level	VProgOff	0		1	V		16
Hold time of VPROG after CLKPROG	tPrgH	0		5	μs		16
Thermal resistance junction-ambient	Rth(j-a)		151		K/W	In still air, soldered on PCB	53

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	Lead finish 100% Sn “matte tin” RHNC Relative humidity (non	7

CAD (KiCad official)

Symbol: AS5040-ASST
Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
3D model: SSOP-16-208mil (KiCad packages3D, STEP)
3D model files: as5040-asst-etched.step / as5040-asst-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); as5040-asst.step / as5040-asst.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: AMS datasheet (61 pp, sha256 20b6fa4b22dc6a84, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF