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AR8035-AL1A

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Qualcomm RF Transceiver ICs, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrf & radioar8035-al1afactory-2.0.0extractor-text

Verified AR8035-AL1A

by Ray · last 7 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

7 Nov 2026RayPublished by the parts factory: tier lcsc, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AR8035-AL1A · QFN-40-EP(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 64-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-2wekf791/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ar8035-al1a.kicad_sym✓ ar8035-al1a.kicad_mod✓ ar8035-al1a.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ar8035-al1a: viewers · Ray
ar8035-al1a-etched.glb Publish 0.1.0 · Ray
ar8035-al1a-etched.step ar8035-al1a: factory component page (tier=lcsc) · Ray
ar8035-al1a-hero.glb ar8035-al1a: hero GLB from the etched model (keeps the MPN mark) · Ray
ar8035-al1a-hero.overlay.json Publish 0.1.0 · Ray
ar8035-al1a.glb Publish 0.1.0 · Ray
ar8035-al1a.kicad_mod Publish 0.1.0 · Ray
ar8035-al1a.kicad_sym Publish 0.1.0 · Ray
ar8035-al1a.lbr Publish 0.1.0 · Ray
ar8035-al1a.step Publish 0.1.0 · Ray
package.json Publish 0.1.1 · Ray
page.json Publish 0.1.1 · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 41 pins · Ray

AR8035-AL1A

Qualcomm · RF Transceiver ICs · QFN-40-EP(5x5)

AR8035-AL1A from Qualcomm, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RSTn input System reset, active low, requires an external pull-up resistor.
2 LX passive Power inductor pin; add an external 4.7 uH power inductor between this pin and pin 38.
3 VDD33 power_in 3.3 V power for the switching regulator.
4 XTLO output Crystal oscillator output, with 27 pF to GND.
5 XTLI input Crystal oscillator input requiring a 27 pF capacitor to GND; supports an external 25 MHz, 1.2 V swing clock input.
6 AVDDL power_in 1.1 V analog power input, connect to pin 38 through a bead.
7 RBIAS passive External 2.37 k 1% resistor to GND sets the bias current.
8 VDDH_REG power_out 2.5 V regulator output, with a 1 uF capacitor connected to this pin.
9 TRXP0 bidirectional Media-dependent interface 0 positive, 100 ohm transmission line.
10 TRXN0 bidirectional Media-dependent interface 0 negative, 100 ohm transmission line.
11 AVDDL power_in 1.1 V analog power input, connect to pin 38 through a bead.
12 TRXP1 bidirectional Media-dependent interface 1 positive, 100 ohm transmission line.
13 TRXN1 bidirectional Media-dependent interface 1 negative, 100 ohm transmission line.
14 AVDD33 power_in Analog 3.3 V power input for the PHY, fed from VDD33 through a bead.
15 TRXP2 bidirectional Media-dependent interface 2 positive, 100 ohm transmission line.
16 TRXN2 bidirectional Media-dependent interface 2 negative, 100 ohm transmission line.
17 AVDDL power_in 1.1 V analog power input, connect to pin 38 through a bead.
18 TRXP3 bidirectional Media-dependent interface 3 positive, 100 ohm transmission line.
19 TRXN3 bidirectional Media-dependent interface 3 negative, 100 ohm transmission line.
20 INT bidirectional Open-drain interrupt signal to the system with internal pull-down, active low by default and needing an external 10K pull-up; can be configured by register as I/O, active high.
21 LED_ACT bidirectional Parallel LED output for 10/100/1000 BASE-T activity (blinking) with internal pull-up; active low if pulled up, active high if pulled down per power-on strapping, also strap PHYADDRESS2.
22 LED_1000 bidirectional Parallel LED output for 1000 BASE-T link with internal pull-up; active low if pulled up, active high if pulled down per power-on strapping, also strap MODE2.
23 CLK_25M output 25 MHz clock output by default with internal pull-down; can be configured for 125, 62.5 or 50 MHz.
24 LED_10_100 bidirectional Parallel LED output for 10/100 BASE-T link with internal pull-up; polarity follows the power-on strapping of LED_1000.
25 RXD3 bidirectional RGMII received data 3 with internal pull-down, also strap MODE3 at power-up.
26 RXD2 bidirectional RGMII received data 2 with internal pull-down, also strap MODE1 at power-up.
27 VDDIO_REG power_out 1.5V/1.8V regulator output; if the RGMII interface level is 2.5V, connect this pin directly to pin 8.
28 RXD1 bidirectional RGMII received data 1 with internal pull-down, also strap PHYADDRESS1 at power-up.
29 RXD0 bidirectional RGMII received data 0 with internal pull-down, also strap PHYADDRESS0 at power-up.
30 RX_DV bidirectional RGMII receive data valid with internal pull-down, also strap MODE0 at power-up.
31 RX_CLK bidirectional 125 MHz RGMII receive clock with internal pull-down, a 22 ohm damping resistor is recommended near the PHY side; also straps the 1.8V/1.5V RGMII I/O level.
32 TX_EN input RGMII transmit enable with internal pull-down.
33 GTX_CLK input RGMII transmit clock, 125 MHz digital, with internal pull-down; a 22 ohm damping resistor near the MAC side is recommended.
34 TXD0 input RGMII transmit data 0 with internal pull-down.
35 TXD1 input RGMII transmit data 1 with internal pull-down.
36 TXD2 input RGMII transmit data 2 with internal pull-down.
37 TXD3 input RGMII transmit data 3 with internal pull-down.
38 DVDDL power_in 1.1 V digital core power input, connect to the power inductor and 10uF+0.1uF ceramic capacitors to GND.
39 MDIO bidirectional Open-drain management data with internal pull-up, needs a 1.5K pull-up to 3.3V/2.5V.
40 MDC input Management data clock reference with internal pull-up.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Qualcomm
Package QFN-40-EP(5x5)
Category RF & Radio
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
RGMII DC input high current IIH 15 A RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC input low current IIL -15 A RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC input high voltage VIH 1.7 3.5 V RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC input low voltage VIL 0.7 V RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC output high voltage VOH 2.4 2.8 V RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC output low voltage VOL 0.4 V RGMII DC characteristics, 2.5/3.3V I/O supply 22
RGMII DC input high voltage VIH 1.4 V RGMII DC characteristics, 1.8V I/O supply 22
RGMII DC input low voltage VIL 0.4 V RGMII DC characteristics, 1.8V I/O supply 22
RGMII DC output high voltage VOH 1.5 V RGMII DC characteristics, 1.8V I/O supply 22
RGMII DC output low voltage VOL 0.3 V RGMII DC characteristics, 1.8V I/O supply 22
RGMII DC input high voltage VIH 1.2 V RGMII DC characteristics, 1.5V I/O supply 22
RGMII DC input low voltage VIL 0.3 V RGMII DC characteristics, 1.5V I/O supply 22
RGMII DC output high voltage VOH 1.3 V RGMII DC characteristics, 1.5V I/O supply 22
RGMII DC output low voltage VOL 0.2 V RGMII DC characteristics, 1.5V I/O supply 22
Data to clock output skew (at Transmitter) TskewT -500 0 500 ps RGMII AC, no internal delay 23
Data to clock output skew (at Receiver) TskewR 1 ns RGMII AC, no internal delay 23
Clock cycle duration Tcyc 7.2 8 8.8 ns RGMII AC, no internal delay 23
Duty cycle for Gigabit Duty_G 45 50 55 % RGMII AC, no internal delay 23
Duty cycle for 10/100T Duty_T 40 50 60 % RGMII AC, no internal delay 23
Rise/Fall time (20 - 80%) Tr/Tf 0.75 ns RGMII AC, no internal delay 23
Data to Clock output Setup (at Transmitter, integrated delay) TsetupT 1.65 2 2.2 ns RGMII AC, with internal delay added (default) 24
Clock to Data output Hold (at Transmitter, integrated delay) TholdT 1.65 2 2.2 ns RGMII AC, with internal delay added (default) 24
Data to Clock input setup (at Receiver, integrated delay) TsetupR 1 2 ns RGMII AC, with internal delay added (default) 24
Data to Clock output setup (at Receiver, integrated delay) TholdR 1 2 ns RGMII AC, with internal delay added (default) 24
MDIO DC input high current IIH 0.4 mA MDIO DC characteristics 24
MDIO DC input low current IIL 0.4 mA MDIO DC characteristics 24
MDIO DC output high voltage VOH 2.4 V MDIO DC characteristics 24
MDIO DC output low voltage VOL 0.4 V MDIO DC characteristics 24
MDIO DC input high voltage VIH 2 V MDIO DC characteristics 24
MDIO DC input low voltage VIL 0.8 V MDIO DC characteristics 24
MDC to MDIO output delay tmdelay 10 30 ns MDIO AC characteristics 25
XI input high level V_IH_XI 0.8 1.2 1.5 V XTAL/OSC characteristic 25
XI input low level voltage V_IL_XI -0.3 0 0.15 V XTAL/OSC characteristic 25
CLK_25M output high voltage 2.3 2.62 2.8 V CLK_25M output characteristics 25
CLK_25M output low voltage 0 0.4 V CLK_25M output characteristics 25
3.3V analog supply voltage VDD33 3.8 V 21
1.1V analog supply voltage AVDD 1.6 V 21
1.1V digital core supply voltage DVDD 1.6 V 21
Storage temperature Tstore -65 150 °C 21
Electrostatic discharge tolerance - Human Body Model HBM -2 2 kV 21
Machine Model electrostatic discharge tolerance MM -200 200 V 21
Charge Device Model electrostatic discharge tolerance CDM -500 500 V 21
3.3V supply voltage VDD33/AVDD33 3.14 3.3 3.47 V 21
1.1V digital core supply voltage AVDDL/DVDDL 1.04 1.1 1.17 V 21
Ambient temperature for normal operation - Commercial chip version TA 0 70 °C Commercial chip version 21
Junction temperature TJ -40 125 °C 21
Thermal Dissipation Coefficient JT 4 C/W 21

CAD (KiCad official)

  • Symbol: AR8035-AL1A
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ar8035-al1a-etched.step / ar8035-al1a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ar8035-al1a.step / ar8035-al1a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Qualcomm datasheet (64 pp, sha256 7ec9611b617621ae, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF