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APM4500AKC-TRG

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Anpec Elec MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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APM4500AKC-TRG

Anpec Elec · MOSFETs · SOP-8

APM4500AKC-TRG from Anpec Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of MOSFET channel 1; the datasheet's absolute maximum ratings apply, with VDSS of 20 V for the N-channel and -20 V for the P-channel device.
2 G1 input Gate terminal of MOSFET channel 1; gate-source voltage is limited to ±12 V (VGSS) per the absolute maximum ratings.
3 S2 passive Source terminal of MOSFET channel 2; the datasheet's absolute maximum ratings apply, with VDSS of 20 V for the N-channel and -20 V for the P-channel device.
4 G2 input Gate terminal of MOSFET channel 2; gate-source voltage is limited to ±12 V (VGSS) per the absolute maximum ratings.
5 D2 passive Drain terminal of MOSFET channel 2 (internally tied to pin 6); drain-source voltage is rated 20 V for the N-channel and -20 V for the P-channel device.
6 D2 passive Drain terminal of MOSFET channel 2 (internally tied to pin 5); drain-source voltage is rated 20 V for the N-channel and -20 V for the P-channel device.
7 D1 passive Drain terminal of MOSFET channel 1 (internally tied to pin 8); drain-source voltage is rated 20 V for the N-channel and -20 V for the P-channel device.
8 D1 passive Drain terminal of MOSFET channel 1 (internally tied to pin 7); drain-source voltage is rated 20 V for the N-channel and -20 V for the P-channel device.

Key specifications

Parameter Value
Manufacturer Anpec Elec
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage (N-Channel) VDSS 20 V 2
Drain-Source Voltage (P-Channel) VDSS -20 V 2
Gate-Source Voltage (N-Channel) VGSS -12 12 V 2
Gate-Source Voltage (P-Channel) VGSS -12 12 V 2
Continuous Drain Current (N-Channel) ID 8 A Surface mounted on 1in2 pad, t≤10sec 2
Continuous Drain Current (P-Channel) ID -4.3 A Surface mounted on 1in2 pad, t≤10sec 2
Pulsed Drain Current (N-Channel) IDM 30 A VGS=10V(N); surface mounted on 1in2 pad, t≤10sec 2
Pulsed Drain Current (P-Channel) IDM -16 A VGS=-10V(P); surface mounted on 1in2 pad, t≤10sec 2
Diode Continuous Forward Current (N-Channel) IS 2.5 A Surface mounted on 1in2 pad, t≤10sec 2
Diode Continuous Forward Current (P-Channel) IS -2 A Surface mounted on 1in2 pad, t≤10sec 2
Maximum Junction Temperature TJ 150 °C 2
Storage Temperature Range TSTG -55 150 °C 2
Power Dissipation PD 2 W TA=25°C; surface mounted on 1in2 pad, t≤10sec 2
Power Dissipation PD 0.8 W TA=100°C; surface mounted on 1in2 pad, t≤10sec 2
Thermal Resistance Junction to Ambient RθJA 62.5 °C/W Surface mounted on 1in2 pad area, t≤10sec 2
Operating Junction Temperature Range -55 150 °C Ordering code suffix C (from ordering information) 1
Drain-Source Breakdown Voltage (N-Channel) BVDSS 20 V VGS=0V, IDS=250μA 2
Drain-Source Breakdown Voltage (P-Channel) BVDSS -20 V VGS=0V, IDS=-250μA 2
Zero Gate Voltage Drain Current (N-Channel) IDSS 1 μA VDS=16V, VGS=0V 2
Zero Gate Voltage Drain Current at TJ=85°C (N-Channel) IDSS 30 μA VDS=16V, VGS=0V, TJ=85°C 2
Zero Gate Voltage Drain Current (P-Channel) IDSS -1 μA VDS=-16V, VGS=0V 2
Zero Gate Voltage Drain Current at TJ=85°C (P-Channel) IDSS -30 μA VDS=-16V, VGS=0V, TJ=85°C 2
Gate Threshold Voltage (N-Channel) VGS(th) 0.5 0.7 1 V VDS=VGS, IDS=250μA 2
Gate Threshold Voltage (P-Channel) VGS(th) -0.5 -0.75 -1 V VDS=VGS, IDS=-250μA 2
Gate Leakage Current (N-Channel) IGSS -10 10 μA VGS=±10V, VDS=0V 2
Gate Leakage Current (P-Channel) IGSS -10 10 μA VGS=±10V, VDS=0V 2
Drain-Source On-State Resistance (N-Channel) RDS(ON) 22 26 mΩ VGS=4.5V, IDS=8A 2
Drain-Source On-State Resistance (P-Channel) RDS(ON) 80 90 mΩ VGS=-4.5V, IDS=-4.3A 2
Drain-Source On-State Resistance (N-Channel) RDS(ON) 30 36 mΩ VGS=2.5V, IDS=5.2A 2
Drain-Source On-State Resistance (P-Channel) RDS(ON) 105 115 mΩ VGS=-2.5V, IDS=-2A 2
Diode Forward Voltage (N-Channel) VSD 0.8 1.3 V ISD=2.5A, VGS=0V 3
Diode Forward Voltage (P-Channel) VSD -0.7 -1.3 V ISD=-2A, VGS=0V 3
Turn-on Delay Time (N-Channel) td(ON) 5 10 ns VDD=10V, RL=10Ω, IDS=1A, VGEN=4.5V, RG=6Ω 3
Turn-on Delay Time (P-Channel) td(ON) 6 12 ns VDD=-10V, RL=10Ω, IDS=-1A, VGEN=-4.5V, RG=6Ω 3
Turn-on Rise Time (N-Channel) tr 11 21 ns VDD=10V, RL=10Ω, IDS=1A, VGEN=4.5V, RG=6Ω 3
Turn-on Rise Time (P-Channel) tr 13 24 ns VDD=-10V, RL=10Ω, IDS=-1A, VGEN=-4.5V, RG=6Ω 3
Turn-off Delay Time (N-Channel) td(OFF) 40 73 ns VDD=10V, RL=10Ω, IDS=1A, VGEN=4.5V, RG=6Ω 3
Turn-off Delay Time (P-Channel) td(OFF) 34 62 ns VDD=-10V, RL=10Ω, IDS=-1A, VGEN=-4.5V, RG=6Ω 3
Turn-off Fall Time (N-Channel) tf 23 42 ns VDD=10V, RL=10Ω, IDS=1A, VGEN=4.5V, RG=6Ω 3
Turn-off Fall Time (P-Channel) tf 32 59 ns VDD=-10V, RL=10Ω, IDS=-1A, VGEN=-4.5V, RG=6Ω 3
Total Gate Charge (N-Channel) Qg 10 13 nC VDS=10V, VGS=4.5V, IDS=8A 3
Total Gate Charge (P-Channel) Qg 6 8 nC VDS=-10V, VGS=-4.5V, IDS=-4.3A 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed 1
contacts tin Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed 1

CAD (KiCad official)

  • Symbol: APM4500AKC-TRG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: apm4500akc-trg-etched.step / apm4500akc-trg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm4500akc-trg.step / apm4500akc-trg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Anpec Elec datasheet (13 pp, sha256 38941cc38e4b7749, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF