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APM32F105RCT6

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Geehy Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersapm32f105rct6factory-2.0.0extractor-text

Verified APM32F105RCT6

by Ray · last 4 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

4 Nov 2026RayPublished by the parts factory: tier lcsc, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: APM32F105RCT6 · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 61-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6n7mw1xr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ apm32f105rct6.kicad_sym✓ apm32f105rct6.kicad_mod✓ apm32f105rct6.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers apm32f105rct6: viewers · Ray
apm32f105rct6-etched.glb Publish 0.1.0 · Ray
apm32f105rct6-etched.step apm32f105rct6: factory component page (tier=lcsc) · Ray
apm32f105rct6-hero.glb apm32f105rct6: hero GLB from the etched model (keeps the MPN mark) · Ray
apm32f105rct6-hero.overlay.json Publish 0.1.0 · Ray
apm32f105rct6.glb Publish 0.1.0 · Ray
apm32f105rct6.kicad_mod Publish 0.1.0 · Ray
apm32f105rct6.kicad_sym Publish 0.1.0 · Ray
apm32f105rct6.lbr Publish 0.1.0 · Ray
apm32f105rct6.step Publish 0.1.0 · Ray
package.json Publish 0.1.1 · Ray
page.json Publish 0.1.1 · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 64 pins · Ray

APM32F105RCT6

Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

APM32F105RCT6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply of 1.8-3.6 V that powers the RTC, the LSE oscillator and the backup registers when VDD is off.
2 PC13-TAMPER-RTC bidirectional Standard I/O on the power-switch domain that can source only 3 mA in total, is limited to 2 MHz output mode with a 30 pF maximum load, must not drive current sources such as LEDs, and defaults to TAMPER_RTC.
3 PC14-OSC32_IN bidirectional Standard I/O on the power-switch domain that defaults to the OSC32_IN LSE input, with the same 3 mA, 2 MHz and 30 pF output limits as PC13.
4 PC15-OSC32_OUT bidirectional Standard I/O on the power-switch domain that defaults to the OSC32_OUT LSE output, with the same 3 mA, 2 MHz and 30 pF output limits as PC13.
5 OSC_IN input High-speed external oscillator input for a 3-25 MHz crystal or ceramic resonator; on LQFP64 it is the default function after reset and can be reassigned to PD0, where output mode is limited to 50 MHz.
6 OSC_OUT output High-speed external oscillator output for a 3-25 MHz crystal or ceramic resonator; on LQFP64 it is the default function after reset and can be reassigned to PD1, where output mode is limited to 50 MHz.
7 NRST bidirectional Active-low reset pin with an internal weak pull-up of 30-50 kΩ, where the input low level is at most 2 V and the input high level is at least 2 V.
8 PC0 bidirectional 3.3 V standard I/O connected directly to the ADC and providing ADC12_IN10.
9 PC1 bidirectional 3.3 V standard I/O connected directly to the ADC and providing ADC12_IN11.
10 PC2 bidirectional 3.3 V standard I/O connected directly to the ADC and providing ADC12_IN12.
11 PC3 bidirectional 3.3 V standard I/O connected directly to the ADC and providing ADC12_IN13.
12 VSSA power_in Analog ground for the ADC, DAC, reset block, RC oscillators and PLL, which must be connected to VSS.
13 VDDA power_in Analog supply of 2.0-3.6 V for the ADC, DAC, reset block, RC oscillators and PLL, which must be at least 2.4 V when the ADC or DAC is used and must be connected to VDD.
14 PA0-WKUP bidirectional 3.3 V standard I/O connected directly to the ADC that provides the WKUP wake-up input (a rising edge wakes the MCU from standby) and ADC12_IN0, with USART2_CTS and timer alternates.
15 PA1 bidirectional 3.3 V standard I/O connected directly to the ADC with USART2_RTS, ADC12_IN1, TMR5_CH2 and TMR2_CH2 alternate functions.
16 PA2 bidirectional 3.3 V standard I/O connected directly to the ADC with USART2_TX, ADC12_IN2, TMR5_CH3 and TMR2_CH3 alternate functions.
17 PA3 bidirectional 3.3 V standard I/O connected directly to the ADC with USART2_RX, ADC12_IN3, TMR5_CH4 and TMR2_CH4 alternate functions.
18 VSS_4 power_in Ground pin for the digital I/O and core supply.
19 VDD_4 power_in Digital supply of 2.0-3.6 V that powers the I/O pins and the internal regulator.
20 PA4 bidirectional 3.3 V standard I/O connected directly to the ADC with default alternates SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4, and remap alternates SPI3_NSS and I2S3_WS.
21 PA5 bidirectional 3.3 V standard I/O connected directly to the ADC with SPI1_SCK, DAC_OUT2 and ADC12_IN5 alternate functions.
22 PA6 bidirectional 3.3 V standard I/O connected directly to the ADC with SPI1_MISO and ADC12_IN6 as default functions, and TMR3_CH1 and TMR1_BKIN as remap alternates.
23 PA7 bidirectional 3.3 V standard I/O connected directly to the ADC with SPI1_MOSI, ADC12_IN7 and TMR3_CH2 as default functions, and TMR1_CH1N as a remap alternate.
24 PC4 bidirectional 3.3 V standard I/O connected directly to the ADC that provides ADC12_IN14.
25 PC5 bidirectional 3.3 V standard I/O connected directly to the ADC that provides ADC12_IN15.
26 PB0 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
27 PB1 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
28 PB2 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
29 PB10 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
30 PB11 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
31 VSS_1 power_in Ground pin for the digital I/O and core supply.
32 VDD_1 power_in Digital supply of 2.0-3.6 V that powers the I/O pins and the internal regulator.
33 PB12 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
34 PB13 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
35 PB14 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
36 PB15 bidirectional I/O pin of port B; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
37 PC6 bidirectional I/O pin of port C; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
38 PC7 bidirectional I/O pin of port C; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
39 PC8 bidirectional I/O pin of port C; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
40 PC9 bidirectional I/O pin of port C; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
41 PA8 bidirectional I/O pin of port A; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
42 PA9 bidirectional I/O pin of port A; it is a floating input after reset and its pull-up/pull-down, push-pull/open-drain and 2/10/50 MHz speed options are set in software, but its alternate-function and structure details are on pages not supplied.
43 PA10 bidirectional I/O pin of port A with a weak pull-up of only 8-15 kΩ (typical 11 kΩ), unlike the 30-50 kΩ on other pins, and its alternate-function details are on pages not supplied.
44 PA11 bidirectional 5 V tolerant I/O (structure 5T) with USART1_CTS, OTG_FS_DM, CAN1_RX and TMR1_CH4 alternate functions, and OTG_FS_ID listed for it.
45 PA12 bidirectional 5 V tolerant I/O (structure 5T) with USART1_RTS, OTG_FS_DP, CAN1_TX and TMR1_ETR alternate functions.
46 PA13 bidirectional 5 V tolerant I/O (structure 5T) that after reset carries the JTMS/SWDIO debug function and can be reassigned to plain PA13.
47 VSS_2 power_in Ground pin for the digital I/O and core supply.
48 VDD_2 power_in Digital supply of 2.0-3.6 V that powers the I/O pins and the internal regulator.
49 PA14 bidirectional 5 V tolerant I/O (structure 5T) that after reset carries the JTCK/SWCLK debug function.
50 PA15 bidirectional 5 V tolerant I/O (structure 5T) that after reset carries the JTDI debug function, with SPI3_NSS and I2S3_WS as default alternates and TMR2_CH1_ETR and SPI1_NSS as remap alternates.
51 PC10 bidirectional 5 V tolerant I/O (structure 5T) with UART4_TX as default alternate and USART3_TX, SPI3_SCK and I2S3_CK as remap alternates.
52 PC11 bidirectional 5 V tolerant I/O (structure 5T) with UART4_RX as default alternate and USART3_RX and SPI3_MISO as remap alternates.
53 PC12 bidirectional 5 V tolerant I/O (structure 5T) with UART5_TX as default alternate and USART3_CK, SPI3_MOSI and I2S3_SD as remap alternates.
54 PD2 bidirectional 5 V tolerant I/O (structure 5T) with TMR3_ETR and UART5_RX alternate functions.
55 PB3 bidirectional 5 V tolerant I/O (structure 5T) that after reset carries the JTDO debug function, with SPI3_SCK and I2S3_CK as default alternates and TRACESWO, TMR2_CH2 and SPI1_SCK as remap alternates.
56 PB4 bidirectional 5 V tolerant I/O (structure 5T) that after reset carries the NJTRST debug function, with SPI3_MISO as default alternate and TMR3_CH1 and SPI1_MISO as remap alternates.
57 PB5 bidirectional 3.3 V standard I/O (structure STD, not 5 V tolerant) with I2C1_SMBAI, SPI3_MOSI and I2S3_SD as default alternates, and TMR3_CH2, SPI1_MOSI and CAN2_RX as remap alternates.
58 PB6 bidirectional 5 V tolerant I/O (structure 5T) with I2C1_SCL and TMR4_CH1 as default alternates, and USART1_TX and CAN2_TX as remap alternates.
59 PB7 bidirectional 5 V tolerant I/O (structure 5T) with I2C1_SDA and TMR4_CH2 as default alternates, and USART1_RX as a remap alternate.
60 BOOT0 input Dedicated boot pin whose high or low level at startup selects main Flash, the built-in bootloader or SRAM as the boot source.
61 PB8 bidirectional 5 V tolerant I/O (structure 5T) with TMR4_CH3 as default alternate, and I2C1_SCL and CAN1_RX as remap alternates.
62 PB9 bidirectional 5 V tolerant I/O (structure 5T) with TMR4_CH4 as default alternate, and I2C1_SDA and CAN1_TX as remap alternates.
63 VSS_3 power_in Ground pin for the digital I/O and core supply.
64 VDD_3 power_in Digital supply of 2.0-3.6 V that powers the I/O pins and the internal regulator.

Key specifications

Parameter Value
Manufacturer Geehy
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal AHB clock frequency fHCLK 96 MHz 29
Internal APB1 clock frequency fPCLK1 48 MHz 29

CAD (KiCad official)

  • Symbol: APM32F105RCT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: apm32f105rct6-etched.step / apm32f105rct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32f105rct6.step / apm32f105rct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Geehy datasheet (61 pp, sha256 cd88d2185f956ac2, retrieved 2026-11-04, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF