component

APM32F103VCT6

Public Made by Adom

by adom

Geehy Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersapm32f103vct6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

APM32F103VCT6

Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

APM32F103VCT6 from Geehy, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Port E general-purpose I/O, FT (5 V tolerant); alternate functions TRACECK/EMMC_A23.
2 PE3 bidirectional Port E general-purpose I/O, FT (5 V tolerant); alternate functions TRACED0/EMMC_A19.
3 PE4 bidirectional Port E general-purpose I/O, FT (5 V tolerant); alternate functions TRACED1/EMMC_A20.
4 PE5 bidirectional Port E general-purpose I/O, FT (5 V tolerant); alternate functions TRACED2/EMMC_A21.
5 PE6 bidirectional Port E general-purpose I/O, FT (5 V tolerant); alternate functions TRACED3/EMMC_A22.
6 VBAT power_in Backup power supply for the RTC, 32 kHz oscillator and backup registers, 1.8 V to 3.6 V.
7 PC13-TAMPER-RTC bidirectional Port C I/O (not FT) with TAMPER-RTC function; as a GPIO it is limited to 3 mA, 2 MHz, 30 pF load per footnote 4.
8 PC14-OSC32_IN bidirectional Port C I/O (not FT) that serves as the 32.768 kHz LSE oscillator input OSC32_IN; same load limits as PC13 per footnote 4.
9 PC15-OSC32_OUT bidirectional Port C I/O (not FT) that serves as the 32.768 kHz LSE oscillator output OSC32_OUT; same load limits as PC13 per footnote 4.
10 VSS_5 power_in Digital ground for the MCU; 0 V reference.
11 VDD_5 power_in Digital supply for I/O and internal regulator, 2 V to 3.6 V.
12 OSC_IN input HSE crystal/resonator oscillator input, 4 MHz to 16 MHz.
13 OSC_OUT output HSE crystal/resonator oscillator output, 4 MHz to 16 MHz.
14 NRST bidirectional Active-low reset pin with internal pull-up (RPU 30 to 53 kΩ); VIL max 0.8 V and VIH min 2 V.
15 PC0 bidirectional Port C I/O (not FT) with ADC123_IN10 analog input.
16 PC1 bidirectional Port C I/O (not FT) with ADC123_IN11 analog input.
17 PC2 bidirectional Port C I/O (not FT) with ADC123_IN12 analog input.
18 PC3 bidirectional Port C I/O (not FT) with ADC123_IN13 analog input.
19 VSSA power_in Analog ground for the ADC, DAC and reference circuits.
20 VREF- power_in ADC/DAC reference ground pin.
21 VREF+ power_in ADC/DAC positive reference input, 2.4 V to VDDA.
22 VDDA power_in Analog supply for ADC, DAC, RC oscillators and PLL, 2.0 V to 3.6 V; the ADC requires 2.4 V to 3.6 V.
23 PA0-WKUP bidirectional Port A I/O with WKUP wake-up function; alternates USART2_CTS, ADC123_IN0, TMR2_CH1_ETR, TMR5_CH1 and TMR_ETR.
24 PA1 bidirectional Port A I/O; alternates USART2_RTS, ADC123_IN1, TMR2_CH2 and TMR5_CH2.
25 PA2 bidirectional Port A I/O; alternates USART2_TX, ADC123_IN2, TMR5_CH3 and TMR2_CH3.
26 PA3 bidirectional Port A I/O; alternates USART2_RX, ADC12_IN3, TMR5_CH4 and TMR2_CH4.
27 VSS_4 power_in Digital ground for the MCU; 0 V reference.
28 VDD_4 power_in Digital supply for I/O and internal regulator, 2 V to 3.6 V.
29 PA4 bidirectional Port A I/O; alternates SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4.
30 PA5 bidirectional Port A I/O; alternates SPI1_SCK, ADC12_IN5 and DAC_OUT1 as printed in the datasheet table.
31 PA6 bidirectional Port A I/O; alternates SPI1_MISO, ADC12_IN6, TMR8_BKIN, TMR3_CH1 and TMR1_BKIN.
32 PA7 bidirectional Port A I/O; alternates SPI1_MOSI, ADC12_IN7, TMR8_CH1N, TMR3_CH2 and TMR1_CH1N.
33 PC4 bidirectional Port C I/O (not FT) with ADC12_IN14 analog input.
34 PC5 bidirectional Port C I/O (not FT) with ADC12_IN15 analog input.
35 PB0 bidirectional Port B I/O (not FT); alternates ADC12_IN8, TMR8_CH2N, TMR3_CH3 and TMR1_CH2N.
36 PB1 bidirectional Port B I/O (not FT); alternates ADC12_IN9, TMR8_CH3N, TMR3_CH4 and TMR1_CH3N.
37 PB2 bidirectional Port B I/O, FT (5 V tolerant); also used as BOOT1.
38 PE7 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D4 and TMR1_ETR.
39 PE8 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D5 and TMR1_CH1N.
40 PE9 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D6 and TMR1_CH1.
41 PE10 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D7 and TMR1_CH2N.
42 PE11 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D8 and TMR1_CH2.
43 PE12 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D9 and TMR1_CH3N.
44 PE13 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D10 and TMR1_CH3.
45 PE14 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D11 and TMR1_CH4.
46 PE15 bidirectional Port E I/O, FT (5 V tolerant); alternates EMMC_D12 and TMR1_BKIN.
47 PB10 bidirectional Port B I/O, FT (5 V tolerant); alternates I2C2_SCL, I2C4_SCL, USART3_TX and TMR2_CH3.
48 PB11 bidirectional Port B I/O, FT (5 V tolerant); alternates I2C2_SDA, I2C4_SDA, USART3_RX and TMR2_CH4.
49 VSS_1 power_in Digital ground for the MCU; 0 V reference.
50 VDD_1 power_in Digital supply for I/O and internal regulator, 2 V to 3.6 V.
51 PB12 bidirectional Port B I/O, FT (5 V tolerant); alternates SPI2_NSS, I2C2_SMBAI, USART3_CK, I2S2_WS and TMR1_BKIN.
52 PB13 bidirectional Port B I/O, FT (5 V tolerant); alternates SPI2_SCK, I2S2_CK, USART3_CTS and TMR1_CH1N.
53 PB14 bidirectional Port B I/O, FT (5 V tolerant); alternates SPI2_MISO, TMR1_CH2N and USART3_RTS.
54 PB15 bidirectional Port B I/O, FT (5 V tolerant); alternates SPI2_MOSI, I2S2_SD and TMR1_CH3N.
55 PD8 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D13 and USART3_TX.
56 PD9 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D14 and USART3_RX.
57 PD10 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D15 and USART3_CK.
58 PD11 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_A16/EMMC_BANK0 and USART3_CTS.
59 PD12 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_A17/EMMC_BANK1, TMR4_CH1 and USART3_RTS.
60 PD13 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_A18 and TMR4_CH2.
61 PD14 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D0 and TMR4_CH3.
62 PD15 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D1 and TMR4_CH4.
63 PC6 bidirectional Port C I/O, FT (5 V tolerant); alternates I2S2_MCK, TMR8_CH1, SDIO_D6 and TMR3_CH1.
64 PC7 bidirectional Port C I/O, FT (5 V tolerant); alternates TMR8_CH2, SDIO_D7 and TMR3_CH2.
65 PC8 bidirectional Port C I/O, FT (5 V tolerant); alternates TMR8_CH3, SDIO_D0 and TMR3_CH3.
66 PC9 bidirectional Port C I/O, FT (5 V tolerant); alternates TMR8_CH4, SDIO_D1 and TMR3_CH4.
67 PA8 bidirectional Port A I/O, FT (5 V tolerant); alternates USART1_CK, TMR1_CH1 and MCO.
68 PA9 bidirectional Port A I/O, FT (5 V tolerant); alternates USART1_TX and TMR1_CH2.
69 PA10 bidirectional Port A I/O, FT (5 V tolerant); alternates USART1_RX and TMR1_CH3.
70 PA11 bidirectional Port A I/O, FT (5 V tolerant); alternates USART1_CTS, USBDDM/USBD2DM, CAN_RX and TMR1_CH4.
71 PA12 bidirectional Port A I/O, FT (5 V tolerant); alternates USART1_RTS, USBDDP/USBD2DP, CAN_TX and TMR1_ETR.
72 PA13 bidirectional Port A I/O, FT (5 V tolerant); alternate function JTMS/SWDIO (SWJ debug).
73 NC unconnected Not connected on the LQFP100 package.
74 VSS_2 power_in Digital ground for the MCU; 0 V reference.
75 VDD_2 power_in Digital supply for I/O and internal regulator, 2 V to 3.6 V.
76 PA14 bidirectional Port A I/O, FT (5 V tolerant); alternate function JTCK/SWCLK (SWJ debug).
77 PA15 bidirectional Port A I/O, FT (5 V tolerant); alternates JTDI, SPI3_NSS, TMR2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional Port C I/O, FT (5 V tolerant); alternates UART4_TX, SDIO_D2 and USART3_TX.
79 PC11 bidirectional Port C I/O, FT (5 V tolerant); alternates UART4_RX, SDIO_D3 and USART3_RX.
80 PC12 bidirectional Port C I/O, FT (5 V tolerant); alternates UART5_TX, SDIO_CK and USART3_CK.
81 PD0 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D2 and CAN_RX, and is a general I/O at up to 50 MHz on LQFP100.
82 PD1 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_D3 and CAN_TX, and is a general I/O at up to 50 MHz on LQFP100.
83 PD2 bidirectional Port D I/O, FT (5 V tolerant); alternates TMR3_ETR, UART5_RX and SDIO_CMD.
84 PD3 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_CLK and USART2_CTS.
85 PD4 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_NOE and USART2_RTS.
86 PD5 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_NWE and USART2_TX.
87 PD6 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_NWAIT and USART2_RX.
88 PD7 bidirectional Port D I/O, FT (5 V tolerant); alternates EMMC_NE1/NCE2 and USART2_CK.
89 PB3 bidirectional Port B I/O, FT (5 V tolerant); alternates JTDO, SPI3_SCK, TRACESWO, TMR2_CH2 and SPI1_SCK.
90 PB4 bidirectional Port B I/O, FT (5 V tolerant); alternates NJTRST, SPI3_MISO, TMR3_CH1 and SPI1_MISO.
91 PB5 bidirectional Port B I/O (not FT); alternates I2C1_SMBAI, TIM4_CH1, TMR3_CH2 and SPI1_MOSI.
92 PB6 bidirectional Port B I/O, FT (5 V tolerant); alternates I2C1_SCL, I2C3_SCL, TMR4_CH1 and USART1_TX.
93 PB7 bidirectional Port B I/O, FT (5 V tolerant); alternates I2C1_SDA, I2C3_SDA, TMR4_CH2, EMMC_NADV and USART1_RX.
94 BOOT0 input Boot mode selection input that selects the boot memory at startup.
95 PB8 bidirectional Port B I/O, FT (5 V tolerant); alternates TMR4_CH3, SDIO_D4, I2C1_SCL, I2C3_SCL and CAN_RX.
96 PB9 bidirectional Port B I/O, FT (5 V tolerant); alternates TMR4_CH4, SDIO_D5, I2C1_SDA, I2C3_SDA and CAN_TX.
97 PE0 bidirectional Port E I/O, FT (5 V tolerant); alternates TMR4_ETR and EMMC_NBL0.
98 PE1 bidirectional Port E I/O, FT (5 V tolerant); alternate function EMMC_NBL1.
99 VSS_3 power_in Digital ground for the MCU; 0 V reference.
100 VDD_3 power_in Digital supply for I/O and internal regulator, 2 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Geehy
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD - VSS VDD - VSS -0.3 4 V 35
Input voltage, 5V-tolerant I/O (FT) VIN -0.3 5.5 V FT I/O; min printed as VSS-0.3 35
Input voltage, other I/O VIN -0.3 V min printed as VSS-0.3; max printed as VDD+0.3 (not numeric) 35
Total current into VDD/VDDA power pins IVDD 150 mA 36
Total current out of VSS ground pins IVSS 150 mA 36
Output current per I/O pin IIO -25 25 mA sink +25 / source -25 per I/O 36
Storage temperature TSTG -55 150 °C 36
Maximum junction temperature TJ 150 °C 36
AHB clock frequency fPCMU (AHB, as printed fHCMU) 0 96 MHz AHB 36
APB1 clock frequency fPCMU1 0 48 MHz APB1 36
APB2 clock frequency fPCMU2 0 96 MHz APB2 36
Supply voltage VDD 2 3.6 V 36
Analog supply voltage VDDA 2 3.6 V 37
Analog supply voltage (ADC in use) VDDA 2.4 3.6 V ADC used 37
Backup supply voltage VBAT 1.8 3.6 V 37
Junction temperature TJ -40 150 °C 37
PVD hysteresis VPVDhyst 107.08 mV 37
POR/PDR threshold (first row of pair) VPOR/PDR 1.86 1.88 1.9 V edge direction not legible in extraction 37
POR/PDR threshold (second row of pair) VPOR/PDR 1.91 1.94 1.96 V edge direction not legible in extraction 37
PDR hysteresis VPDRhyst 38.19 55.33 72.47 mV PDR 37
Reset temporization TRSTTEMPO 1.47 ms 37
Internal reference voltage VREFINT 1.2 1.21 1.22 V VDD = 2-3.6 V 38
ADC sampling time for VREFINT TS_vrefint 5.1 17.1 38
VREFINT temperature coefficient Tcoeff 104 ppm/°C 38
HSE oscillator frequency fOSC_IN 4 8 16 MHz HSE 4~16MHz 44
HSE startup time tSU(HSE) 0.6 0.96 1.33 ms HSE 8MHz, VDD=3.3V (footnote 4) 44
LSE startup time tSU(LSE) 0.62 1.32 2.02 s TA=105, VDD=2-3.6V 45
LSE startup time tSU(LSE) 0.47 1.17 1.86 s TA=25, VDD=3.3V 45
LSE startup time tSU(LSE) 0.32 4.32 8.32 s TA=-40, VDD=3.3V 45
HSI frequency accuracy ACCHSI -1 1 % VDD = 3.3V 46
HSI frequency accuracy ACCHSI -2.76 2.3 % VDD = 3.3V 46
HSI frequency accuracy ACCHSI -2.76 2.45 % VDD = 2-3.6V 46
LSI frequency fLSI 36.74 41.5 46.26 KHz VDD = 2-3.6V 46
PLL input frequency fPLL_IN 1 8 25 MHz 47
PLL input duty cycle 40 60 % 47
PLL output frequency fPLL_OUT 2 96 MHz VDD = 3.3V 47
Flash programming time (16-bit) tprog 33.7 37.1 40.5 µs VDD=2.4~3.6V 47
Flash page erase time (1Kbytes) tERASE 3.5 3.11 3.5 ms 1Kbytes, VDD=2.4~3.6V 47
Flash mass erase time tME 25.4 26.5 27.7 ms VDD=3.3V 47
Flash programming voltage Vprog 2 3.3 3.6 V 47
Low-level input voltage, TTL I/O VIL -0.5 0.8 V TTL, VCC=2.7~3.6V 50
High-level input voltage, I/O VIH 2 V max printed as VDD+0.5 (not numeric) 50
High-level input voltage, FT I/O VIH 2 5.5 V FT I/O 50
Low-level input voltage, CMOS I/O VIL -0.5 V max printed as 0.3VDD (not numeric) 50
Weak pull-up resistance RPU 32 40 49 VIN = VSS 50
Weak pull-down resistance RPD 32 40 49 VIN = VDD 50
Output low voltage, TTL 8 mA I/O VOL 0.4 V 8 TTL, IIO=+8mA, 2.7V<VDD<3.6V 51
Output low voltage, CMOS 8 mA I/O VOL 0.4 V 8 CMOS, IIO=+8mA, 2.7V<VDD<3.6V 51
Output high voltage, 8 mA I/O VOH 2.4 V 8 mA, footnote (2) 51
Output low voltage, 20 mA I/O VOL 1.3 V IIO=+20mA, 2.7V<VDD<3.6V 51
NRST low-level input voltage VIL(NRST) -0.5 0.8 V VCC=3.3V 53
NRST high-level input voltage VIH(NRST) 2 V max printed as VDD+0.5 (not numeric) 53
NRST pull-up resistance RPU 30 40 53 VIN = VSS 53
USB supply voltage VDD 3 3.6 V USB, VDD = 3.0~3.6V 56
USB output low voltage VOL 0.3 V 1.5k RL to 3.6V 57
USB output high voltage VOH 2.8 3.6 V 15k RL to VSS 57

CAD (KiCad official)

  • Symbol: APM32F103VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: apm32f103vct6-etched.step / apm32f103vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32f103vct6.step / apm32f103vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Geehy datasheet (75 pp, sha256 6b7b3dc839daa1d7, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF