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APM32F103VBT6

Public Made by Adom

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Geehy Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersapm32f103vbt6factory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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APM32F103VBT6

Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

APM32F103VBT6 from Geehy, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO port E pin PE2, 5 V tolerant (FT); default function PE2, alternate function TRACECK for trace clock.
2 PE3 bidirectional GPIO port E pin PE3, 5 V tolerant (FT); default function PE3, alternate function TRACED0.
3 PE4 bidirectional GPIO port E pin PE4, 5 V tolerant (FT); default function PE4, alternate function TRACED1.
4 PE5 bidirectional GPIO port E pin PE5, 5 V tolerant (FT); default function PE5, alternate function TRACED2.
5 PE6 bidirectional GPIO port E pin PE6, 5 V tolerant (FT); default function PE6, alternate function TRACED3.
6 VBAT power_in Backup supply for RTC, the external 32.768 kHz oscillator and backup registers when VDD is off; 1.6 V to 3.6 V per Table 15.
7 PC13-TAMPER-RTC bidirectional PC13 I/O with TAMPER-RTC function; weak drive: only one of PC13-PC15 may be an output at a time, 2 MHz mode only, maximum 30 pF load, and it cannot source current such as driving an LED.
8 PC14-OSC32_IN bidirectional PC14 I/O with OSC32_IN function (32.768 kHz oscillator input); weak drive: only one of PC13-PC15 may be an output at a time, 2 MHz mode only, maximum 30 pF load, and no current-source use.
9 PC15-OSC32_OUT bidirectional PC15 I/O with OSC32_OUT function (32.768 kHz oscillator output); weak drive: only one of PC13-PC15 may be an output at a time, 2 MHz mode only, maximum 30 pF load, and no current-source use.
10 VSS_5 power_in Ground pin for the digital supply domain; must be connected to the board ground.
11 VDD_5 power_in Digital supply pin, 2.0 V to 3.6 V; directly supplies the I/O and, through the voltage regulator, the core.
12 OSC_IN input HSE oscillator input for a 4-16 MHz crystal or ceramic resonator, with load capacitors placed close to the pins.
13 OSC_OUT output HSE oscillator output for a 4-16 MHz crystal or ceramic resonator.
14 NRST bidirectional Active-low reset pin; CMOS input with a permanent internal pull-up of 32-49 kOhm, VIL max 0.8 V, VIH min 2 V.
15 PC0 bidirectional GPIO port C pin PC0, alternate function ADC12_IN10 analog input.
16 PC1 bidirectional GPIO port C pin PC1, alternate function ADC12_IN11 analog input.
17 PC2 bidirectional GPIO port C pin PC2, alternate function ADC12_IN12 analog input.
18 PC3 bidirectional GPIO port C pin PC3, alternate function ADC12_IN13 analog input.
19 VSSA power_in Analog ground for the ADC, reset block, RC oscillators and PLL; must be connected to VSS.
20 VREF- power_in ADC negative reference voltage pin.
21 VREF+ power_in ADC positive reference voltage; 2.4 V up to VDDA.
22 VDDA power_in Analog supply for the ADC, reset block, RC oscillators and PLL; 2.4 V to 3.6 V when ADC is used, 2 V to 3.6 V otherwise, and must be connected to VDD.
23 PA0-WKUP bidirectional GPIO port A pin PA0; default function PA0, alternate functions WKUP (wake-up), USART2_CTS, ADC12_IN0 and TMR2_CH1_ETR.
24 PA1 bidirectional GPIO port A pin PA1; alternate functions USART2_RTS, ADC12_IN1 and TMR2_CH2.
25 PA2 bidirectional GPIO port A pin PA2; alternate functions USART2_TX, ADC12_IN2 and TMR2_CH3.
26 PA3 bidirectional GPIO port A pin PA3; alternate functions USART2_RX, ADC12_IN3 and TMR2_CH4.
27 VSS_4 power_in Ground pin for the digital supply domain; must be connected to the board ground.
28 VDD_4 power_in Digital supply pin, 2.0 V to 3.6 V; directly supplies the I/O and, through the voltage regulator, the core.
29 PA4 bidirectional GPIO port A pin PA4; alternate functions SPI1_NSS, USART2_CK and ADC12_IN4.
30 PA5 bidirectional GPIO port A pin PA5; alternate functions SPI1_SCK and ADC12_IN5.
31 PA6 bidirectional GPIO port A pin PA6, 5 V tolerant (FT); alternate functions SPI1_MISO, ADC12_IN6, TMR3_CH1 and TMR1_BKIN.
32 PA7 bidirectional GPIO port A pin PA7, 5 V tolerant (FT); alternate functions SPI1_MOSI, ADC12_IN7, TMR3_CH2 and TMR1_CH1N.
33 PC4 bidirectional GPIO port C pin PC4, alternate function ADC12_IN14 analog input.
34 PC5 bidirectional GPIO port C pin PC5, alternate function ADC12_IN15 analog input.
35 PB0 bidirectional GPIO port B pin PB0; alternate functions ADC12_IN8, TMR3_CH3 and TMR1_CH2N.
36 PB1 bidirectional GPIO port B pin PB1; alternate functions ADC12_IN9, TMR3_CH4 and TMR1_CH3N.
37 PB2/BOOT1 bidirectional GPIO port B pin PB2, 5 V tolerant (FT); also used as BOOT1 boot-mode configuration.
38 PE7 bidirectional GPIO port E pin PE7, 5 V tolerant (FT); alternate function TMR1_ETR.
39 PE8 bidirectional GPIO port E pin PE8, 5 V tolerant (FT); alternate function TMR1_CH1N.
40 PE9 bidirectional GPIO port E pin PE9, 5 V tolerant (FT); alternate function TMR1_CH1.
41 PE10 bidirectional GPIO port E pin PE10, 5 V tolerant (FT); alternate function TMR1_CH2N.
42 PE11 bidirectional GPIO port E pin PE11, 5 V tolerant (FT); alternate function TMR1_CH2.
43 PE12 bidirectional GPIO port E pin PE12, 5 V tolerant (FT); alternate function TMR1_CH3N.
44 PE13 bidirectional GPIO port E pin PE13, 5 V tolerant (FT); alternate function TMR1_CH3.
45 PE14 bidirectional GPIO port E pin PE14, 5 V tolerant (FT); alternate function TMR1_CH4.
46 PE15 bidirectional GPIO port E pin PE15, 5 V tolerant (FT); alternate function TMR1_BKIN.
47 PB10 bidirectional GPIO port B pin PB10, 5 V tolerant (FT); alternate functions I2C2_SCL, I2C4_SCL, USART3_TX and TMR2_CH3.
48 PB11 bidirectional GPIO port B pin PB11, 5 V tolerant (FT); alternate functions I2C2_SDA, I2C4_SDA, USART3_RX and TMR2_CH4.
49 VSS_1 power_in Ground pin for the digital supply domain; must be connected to the board ground.
50 VDD_1 power_in Digital supply pin, 2.0 V to 3.6 V; directly supplies the I/O and, through the voltage regulator, the core.
51 PB12 bidirectional GPIO port B pin PB12, 5 V tolerant (FT); alternate functions SPI2_NSS, I2C2_SMBAI, USART3_CK and TMR1_BKIN.
52 PB13 bidirectional GPIO port B pin PB13, 5 V tolerant (FT); alternate functions SPI2_SCK, USART3_CTS, TMR1_CH1N and QSPI_IO0.
53 PB14 bidirectional GPIO port B pin PB14, 5 V tolerant (FT); alternate functions SPI2_MISO, USART3_RTS, TMR1_CH2N and QSPI_IO1.
54 PB15 bidirectional GPIO port B pin PB15, 5 V tolerant (FT); alternate functions SPI2_MOSI, TMR1_CH3N and QSPI_IO2.
55 PD8 bidirectional GPIO port D pin PD8, 5 V tolerant (FT); alternate functions QSPI_IO3 and USART3_TX.
56 PD9 bidirectional GPIO port D pin PD9, 5 V tolerant (FT); alternate function USART3_RX.
57 PD10 bidirectional GPIO port D pin PD10, 5 V tolerant (FT); alternate functions QSPI_CLK and USART3_CK.
58 PD11 bidirectional GPIO port D pin PD11, 5 V tolerant (FT); alternate function USART3_CTS.
59 PD12 bidirectional GPIO port D pin PD12, 5 V tolerant (FT); alternate functions QSPI_SS_N, TMR4_CH1 and USART3_RTS.
60 PD13 bidirectional GPIO port D pin PD13, 5 V tolerant (FT); alternate function TMR4_CH2.
61 PD14 bidirectional GPIO port D pin PD14, 5 V tolerant (FT); alternate function TMR4_CH3.
62 PD15 bidirectional GPIO port D pin PD15, 5 V tolerant (FT); alternate function TMR4_CH4.
63 PC6 bidirectional GPIO port C pin PC6, 5 V tolerant (FT); alternate function TMR3_CH1.
64 PC7 bidirectional GPIO port C pin PC7, 5 V tolerant (FT); alternate function TMR3_CH2.
65 PC8 bidirectional GPIO port C pin PC8, 5 V tolerant (FT); alternate function TMR3_CH3.
66 PC9 bidirectional GPIO port C pin PC9, 5 V tolerant (FT); alternate function TMR3_CH4.
67 PA8 bidirectional GPIO port A pin PA8, 5 V tolerant (FT); alternate functions USART1_CK, TMR1_CH1 and MCO (microcontroller clock output).
68 PA9 bidirectional GPIO port A pin PA9, 5 V tolerant (FT); alternate functions USART1_TX and TMR1_CH2.
69 PA10 bidirectional GPIO port A pin PA10, 5 V tolerant (FT); alternate functions USART1_RX and TMR1_CH3.
70 PA11 bidirectional GPIO port A pin PA11, 5 V tolerant (FT); alternate functions USART1_CTS, USBD1DM, USBD2DM, CAN_RX and TMR1_CH4; used by USBD when USB is enabled.
71 PA12 bidirectional GPIO port A pin PA12, 5 V tolerant (FT); alternate functions USART1_RTS, USBD1DP, USBD2DP, CAN_TX and TMR1_ETR; used by USBD when USB is enabled.
72 PA13 bidirectional GPIO port A pin PA13, 5 V tolerant (FT); default function JTMS/SWDIO (JTAG/SWD debug data line).
73 NC unconnected Not connected (未连接) on the LQFP100 package.
74 VSS_2 power_in Ground pin for the digital supply domain; must be connected to the board ground.
75 VDD_2 power_in Digital supply pin, 2.0 V to 3.6 V; directly supplies the I/O and, through the voltage regulator, the core.
76 PA14 bidirectional GPIO port A pin PA14, 5 V tolerant (FT); default function JTCK/SWCLK (JTAG/SWD clock).
77 PA15 bidirectional GPIO port A pin PA15, 5 V tolerant (FT); default function JTDI, alternate functions TMR2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional GPIO port C pin PC10, 5 V tolerant (FT); alternate function USART3_TX.
79 PC11 bidirectional GPIO port C pin PC11, 5 V tolerant (FT); alternate function USART3_RX.
80 PC12 bidirectional GPIO port C pin PC12, 5 V tolerant (FT); alternate function USART3_CK.
81 PD0 bidirectional GPIO port D pin PD0, 5 V tolerant (FT); on LQFP100 PD0 is an inherent functional pin (not OSC_IN); alternate function CAN_RX.
82 PD1 bidirectional GPIO port D pin PD1, 5 V tolerant (FT); on LQFP100 PD1 is an inherent functional pin (not OSC_OUT); alternate function CAN_TX.
83 PD2 bidirectional GPIO port D pin PD2, 5 V tolerant (FT); alternate function TMR3_ETR.
84 PD3 bidirectional GPIO port D pin PD3, 5 V tolerant (FT); alternate function USART2_CTS.
85 PD4 bidirectional GPIO port D pin PD4, 5 V tolerant (FT); alternate function USART2_RTS.
86 PD5 bidirectional GPIO port D pin PD5, 5 V tolerant (FT); alternate function USART2_TX.
87 PD6 bidirectional GPIO port D pin PD6, 5 V tolerant (FT); alternate function USART2_RX.
88 PD7 bidirectional GPIO port D pin PD7, 5 V tolerant (FT); alternate function USART2_CK.
89 PB3 bidirectional GPIO port B pin PB3, 5 V tolerant (FT); default function JTDO, alternate functions TRACESWO, TMR2_CH2 and SPI1_SCK.
90 PB4 bidirectional GPIO port B pin PB4, 5 V tolerant (FT); default function NJTRST, alternate functions TMR3_CH1 and SPI1_MISO.
91 PB5 bidirectional GPIO port B pin PB5 (not marked 5 V tolerant in Table 8); alternate functions I2C1_SMBAI, TMR3_CH2 and SPI1_MOSI.
92 PB6 bidirectional GPIO port B pin PB6, 5 V tolerant (FT); alternate functions I2C1_SCL, I2C3_SCL, TMR4_CH1 and USART1_TX.
93 PB7 bidirectional GPIO port B pin PB7, 5 V tolerant (FT); alternate functions I2C1_SDA, I2C3_SDA, TMR4_CH2 and USART1_RX.
94 BOOT0 input Boot mode selection input sampled at startup to choose user flash, system memory or internal SRAM boot.
95 PB8 bidirectional GPIO port B pin PB8, 5 V tolerant (FT); alternate functions TMR4_CH3, I2C1_SCL, I2C3_SCL and CAN_RX.
96 PB9 bidirectional GPIO port B pin PB9, 5 V tolerant (FT); alternate functions TMR4_CH4, I2C1_SDA, I2C3_SDA and CAN_TX.
97 PE0 bidirectional GPIO port E pin PE0, 5 V tolerant (FT); alternate function TMR4_ETR.
98 PE1 bidirectional GPIO port E pin PE1, 5 V tolerant (FT); no alternate function listed in Table 8.
99 VSS_3 power_in Ground pin for the digital supply domain; must be connected to the board ground.
100 VDD_3 power_in Digital supply pin, 2.0 V to 3.6 V; directly supplies the I/O and, through the voltage regulator, the core.

Key specifications

Parameter Value
Manufacturer Geehy
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
USBD operating voltage VDD 3 3.6 V 56
Differential input sensitivity (USBDP, USBDM) VDI 0.2 V 56
Differential common-mode range VCM 0.8 2.5 V 包含 VDI范围 56
Single-ended receiver threshold VSE 1.3 2 V 56
Static output low level VOL 0.3 V 1.5kΩ的 RL接至 3.6V 56
Static output high level VOH 2.8 3.6 V 15kΩ的 RL接至 VSS 56
Rise time tr 4.6 9.3 ns CL = 50pF 57
Fall time tf 5.2 10.9 ns CL = 50pF 57
Rise/fall time matching tr/tf trfm 71 97 % 57
Output signal crossover voltage VCRS 1.6 2.17 V 57
ADC supply voltage VDDA 2.4 3.6 V 57
ADC positive reference voltage VREF+ 2.4 V 57
Current into VREF input pin IVREF 260 484 μA 57
ADC clock frequency fADC 0.6 14 MHz 57
Sampling rate fS 0.05 1 MHz 57
Conversion voltage range VAIN 0 V 57
Sampling time tS 0.107 17.1 μs fADC = 14MHz 57
Sampling time tS 1.5 239.5 1/fADC 57
Total conversion time (including sampling time) tCONV 1 18 μs fADC = 14MHz 57
Total conversion time (including sampling time) tCONV 14 252 1/fADC 57
Maximum external input impedance RAIN RAIN 1.2 kΩ TS = 1.5 cycles, tS = 0.11 μs 58
Maximum external input impedance RAIN RAIN 10 kΩ TS = 7.5 cycles, tS = 0.54 μs 58
Maximum external input impedance RAIN RAIN 19 kΩ TS = 13.5 cycles, tS = 0.96 μs 58
Maximum external input impedance RAIN RAIN 41 kΩ TS = 28.5 cycles, tS = 2.04 μs 58
Maximum external input impedance RAIN RAIN 60 kΩ TS = 41.5 cycles, tS = 2.96 μs 58
Maximum external input impedance RAIN RAIN 80 kΩ TS = 55.5 cycles, tS = 3.96 μs 58
Maximum external input impedance RAIN RAIN 104 kΩ TS = 71.5 cycles, tS = 5.11 μs 58
Maximum external input impedance RAIN RAIN 350 kΩ TS = 239.5 cycles, tS = 17.1 μs 58
Overall (total) ADC error ET -5.5 2.5 5.5 LSB fPCLK2=56MHz, fADC=14MHz, RAIN<10KΩ 58
Offset error Eo -3.5 2.1 3.5 LSB 58
Supply voltage VDD VDD 2 3.6 V 12
Analog supply voltage VDDA VDDA 2.4 3.6 V 12
Backup supply voltage VBAT VBAT 1.8 3.6 V 12

CAD (KiCad official)

  • Symbol: APM32F103VBT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: apm32f103vbt6-etched.step / apm32f103vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32f103vbt6.step / apm32f103vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Geehy datasheet (85 pp, sha256 8c9a2ab3889a585a, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF