APM32F103RET6

Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

APM32F103RET6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup-domain supply for the RTC and backup registers, specified at 1.8 to 3.6 V.
2	PC13-TAMPER-RTC	bidirectional	GPIO PC13 with TAMPER-RTC function; output drive is limited (footnote 4: 3 mA, 2 MHz, 30 pF).
3	PC14-OSC32_IN	bidirectional	GPIO PC14 that serves as the 32.768 kHz LSE oscillator input OSC32_IN, with the same limited drive as PC13.
4	PC15-OSC32_OUT	bidirectional	GPIO PC15 that serves as the 32.768 kHz LSE oscillator output OSC32_OUT, with the same limited drive as PC13.
5	PD0-OSC_IN	input	High-speed external oscillator input OSC_IN (4 to 16 MHz HSE) on LQFP64; PD0 GPIO is not available on this pin in this package.
6	PD1-OSC_OUT	output	High-speed external oscillator output OSC_OUT for the 4 to 16 MHz HSE crystal on LQFP64; PD1 GPIO is not available on this pin in this package.
7	NRST	bidirectional	Active-low reset pin with internal pull-up of 30 to 53 kΩ and about 300 mV Schmitt hysteresis.
8	PC0	bidirectional	GPIO PC0 that can be used as ADC123 analog input channel 10 (ADC123_IN10).
9	PC1	bidirectional	GPIO PC1 that can be used as ADC123 analog input channel 11 (ADC123_IN11).
10	PC2	bidirectional	GPIO PC2 that can be used as ADC123 analog input channel 12 (ADC123_IN12).
11	PC3	bidirectional	GPIO PC3 that can be used as ADC123 analog input channel 13 (ADC123_IN13).
12	VSSA	power_in	Analog ground for the ADC, DAC and analog circuits.
13	VDDA	power_in	Analog supply, 2.0 to 3.6 V; the ADC and DAC require VDDA of at least 2.4 V.
14	PA0-WKUP	bidirectional	GPIO PA0 that also provides the WKUP wake-up input, ADC123_IN0, USART2_CTS and timer functions.
15	PA1	bidirectional	GPIO PA1 with USART2_RTS, ADC123_IN1, TMR2_CH2 and TMR5_CH2 alternate functions.
16	PA2	bidirectional	GPIO PA2 with USART2_TX, ADC123_IN2, TMR5_CH3 and TMR2_CH3 alternate functions.
17	PA3	bidirectional	GPIO PA3 with USART2_RX, ADC12_IN3, TMR5_CH4 and TMR2_CH4 alternate functions.
18	VSS_4	power_in	Digital ground.
19	VDD_4	power_in	Digital supply, 2.0 to 3.6 V.
20	PA4	bidirectional	GPIO PA4 with SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4 alternate functions.
21	PA5	bidirectional	GPIO PA5 with SPI1_SCK, ADC12_IN5 and DAC_OUT1 alternate functions.
22	PA6	bidirectional	GPIO PA6 with SPI1_MISO, ADC12_IN6, TMR8_BKIN, TMR3_CH1 and TMR1_BKIN alternate functions.
23	PA7	bidirectional	GPIO PA7 with SPI1_MOSI, ADC12_IN7, TMR8_CH1N, TMR3_CH2 and TMR1_CH1N alternate functions.
24	PC4	bidirectional	GPIO PC4 that can be used as ADC12 analog input channel 14 (ADC12_IN14).
25	PC5	bidirectional	GPIO PC5 that can be used as ADC12 analog input channel 15 (ADC12_IN15).
26	PB0	bidirectional	GPIO PB0 with ADC12_IN8, TMR8_CH2N, TMR3_CH3 and TMR1_CH2N alternate functions.
27	PB1	bidirectional	GPIO PB1 with ADC12_IN9, TMR8_CH3N, TMR3_CH4 and TMR1_CH3N alternate functions.
28	PB2/BOOT1	bidirectional	5 V tolerant GPIO PB2 that is also sampled as the BOOT1 boot-mode pin.
29	PB10	bidirectional	5 V tolerant GPIO PB10 with I2C2_SCL, I2C4_SCL, USART3_TX and TMR2_CH3 alternate functions.
30	PB11	bidirectional	5 V tolerant GPIO PB11 with I2C2_SDA, I2C4_SDA, USART3_RX and TMR2_CH4 alternate functions.
31	VSS_1	power_in	Digital ground.
32	VDD_1	power_in	Digital supply, 2.0 to 3.6 V.
33	PB12	bidirectional	5 V tolerant GPIO PB12 with SPI2_NSS, I2C2_SMBAI, USART3_CK, I2S2_WS and TMR1_BKIN alternate functions.
34	PB13	bidirectional	5 V tolerant GPIO PB13 with SPI2_SCK, I2S2_CK, USART3_CTS and TMR1_CH1N alternate functions.
35	PB14	bidirectional	5 V tolerant GPIO PB14 with SPI2_MISO, TMR1_CH2N and USART3_RTS alternate functions.
36	PB15	bidirectional	5 V tolerant GPIO PB15 with SPI2_MOSI, I2S2_SD and TMR1_CH3N alternate functions.
37	PC6	bidirectional	5 V tolerant GPIO PC6 with I2S2_MCK, TMR8_CH1, SDIO_D6 and TMR3_CH1 alternate functions.
38	PC7	bidirectional	5 V tolerant GPIO PC7 with TMR8_CH2, SDIO_D7 and TMR3_CH2 alternate functions.
39	PC8	bidirectional	5 V tolerant GPIO PC8 with TMR8_CH3, SDIO_D0 and TMR3_CH3 alternate functions.
40	PC9	bidirectional	5 V tolerant GPIO PC9 with TMR8_CH4, SDIO_D1 and TMR3_CH4 alternate functions.
41	PA8	bidirectional	5 V tolerant GPIO PA8 with USART1_CK, TMR1_CH1 and MCO alternate functions.
42	PA9	bidirectional	5 V tolerant GPIO PA9 with USART1_TX and TMR1_CH2 alternate functions.
43	PA10	bidirectional	5 V tolerant GPIO PA10 with USART1_RX and TMR1_CH3 alternate functions.
44	PA11	bidirectional	5 V tolerant GPIO PA11 with USART1_CTS, USBDDM/USBD2DM, CAN_RX and TMR1_CH4 alternate functions.
45	PA12	bidirectional	5 V tolerant GPIO PA12 with USART1_RTS, USBDDP/USBD2DP, CAN_TX and TMR1_ETR alternate functions.
46	PA13	bidirectional	5 V tolerant GPIO PA13 that serves as the JTMS/SWDIO serial-wire debug data pin.
47	VSS_2	power_in	Digital ground.
48	VDD_2	power_in	Digital supply, 2.0 to 3.6 V.
49	PA14	bidirectional	5 V tolerant GPIO PA14 that serves as the JTCK/SWCLK serial-wire debug clock pin.
50	PA15	bidirectional	5 V tolerant GPIO PA15 with JTDI, SPI3_NSS, TMR2_CH1_ETR and SPI1_NSS alternate functions.
51	PC10	bidirectional	5 V tolerant GPIO PC10 with UART4_TX, SDIO_D2 and USART3_TX alternate functions.
52	PC11	bidirectional	5 V tolerant GPIO PC11 with UART4_RX, SDIO_D3 and USART3_RX alternate functions.
53	PC12	bidirectional	5 V tolerant GPIO PC12 with UART5_TX, SDIO_CK and USART3_CK alternate functions.
54	PD2	bidirectional	5 V tolerant GPIO PD2 with TMR3_ETR, UART5_RX and SDIO_CMD alternate functions.
55	PB3	bidirectional	5 V tolerant GPIO PB3 with JTDO, SPI3_SCK, TRACESWO, TMR2_CH2 and SPI1_SCK alternate functions.
56	PB4	bidirectional	5 V tolerant GPIO PB4 with NJTRST, SPI3_MISO, TMR3_CH1 and SPI1_MISO alternate functions.
57	PB5	bidirectional	GPIO PB5 with I2C1_SMBAI, TIM4_CH1, TMR3_CH2 and SPI1_MOSI alternate functions; not listed as 5 V tolerant.
58	PB6	bidirectional	5 V tolerant GPIO PB6 with I2C1_SCL, I2C3_SCL, TMR4_CH1 and USART1_TX alternate functions.
59	PB7	bidirectional	5 V tolerant GPIO PB7 with I2C1_SDA, I2C3_SDA, TMR4_CH2 and USART1_RX alternate functions.
60	BOOT0	input	Boot-mode selection input BOOT0, which together with BOOT1 (PB2) selects the boot memory source.
61	PB8	bidirectional	5 V tolerant GPIO PB8 with TMR4_CH3, SDIO_D4, I2C1_SCL, I2C3_SCL and CAN_RX alternate functions.
62	PB9	bidirectional	5 V tolerant GPIO PB9 with TMR4_CH4, SDIO_D5, I2C1_SDA, I2C3_SDA and CAN_TX alternate functions.
63	VSS_3	power_in	Digital ground.
64	VDD_3	power_in	Digital supply, 2.0 to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	Geehy
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD-VSS (absolute max)	VDD - VSS	-0.3		4	V		35
Input voltage on five-volt tolerant pin	VIN	-0.3		5.5	V	FT (5V tolerant) pins; printed min is VSS-0.3	35
Input voltage on other pins	VIN	-0.3			V	printed max is VDD+0.3; printed min is VSS-0.3	35
Variation between VDDx and VDD	/VDDx - VDD/			50	mV		35
Total current into VDD/VDDA power lines	IVDD			150	mA		36
Total current out of VSS ground lines	IVSS			150	mA		36
Output current sunk/sourced by any I/O and control pin	IIO	-25		25	mA		36
Storage temperature range	TSTG	-55		150	°C		36
Maximum junction temperature (absolute)	TJ			150	°C		36
Internal AHB clock frequency	fHCLK	0		96	MHz		36
APB1 clock frequency	fPCLK1	0		48	MHz		36
APB2 clock frequency	fPCLK2	0		96	MHz		36
Supply voltage	VDD	2		3.6	V		36
Analog supply voltage	VDDA	2		3.6	V		37
Analog supply voltage for ADC	VDDA	2.4		3.6	V	ADC used	37
Backup supply voltage	VBAT	1.8		3.6	V		37
Junction operating temperature	TJ	-40		150	°C		37
PVD threshold, PLS[2:0]=000, first row of pair	VPVD	2.16	2.19	2.22	V	-40°C<TA<+105°C; PLS[2:0]=000; edge label not legible	37
PVD threshold, PLS[2:0]=000, second row of pair	VPVD	2.06	2.09	2.11	V	-40°C<TA<+105°C; PLS[2:0]=000; edge label not legible	37
PVD threshold, PLS[2:0]=001, first row of pair	VPVD	2.26	2.29	2.32	V	-40°C<TA<+105°C; PLS[2:0]=001; edge label not legible	37
PVD threshold, PLS[2:0]=001, second row of pair	VPVD	2.15	2.18	2.21	V	-40°C<TA<+105°C; PLS[2:0]=001; edge label not legible	37
PVD threshold, PLS[2:0]=010, first row of pair	VPVD	2.36	2.39	2.42	V	-40°C<TA<+105°C; PLS[2:0]=010; edge label not legible	37
PVD threshold, PLS[2:0]=010, second row of pair	VPVD	2.25	2.28	2.31	V	-40°C<TA<+105°C; PLS[2:0]=010; edge label not legible	37
PVD threshold, PLS[2:0]=011, first row of pair	VPVD	2.45	2.49	2.52	V	-40°C<TA<+105°C; PLS[2:0]=011; edge label not legible	37
PVD threshold, PLS[2:0]=011, second row of pair	VPVD	2.35	2.38	2.41	V	-40°C<TA<+105°C; PLS[2:0]=011; edge label not legible	37
PVD threshold, PLS[2:0]=100, first row of pair	VPVD	2.55	2.59	2.62	V	-40°C<TA<+105°C; PLS[2:0]=100; edge label not legible	37
PVD threshold, PLS[2:0]=100, second row of pair	VPVD	2.44	2.48	2.51	V	-40°C<TA<+105°C; PLS[2:0]=100; edge label not legible	37
PVD threshold, PLS[2:0]=101, first row of pair	VPVD	2.65	2.68	2.72	V	-40°C<TA<+105°C; PLS[2:0]=101; edge label not legible	37
PVD threshold, PLS[2:0]=101, second row of pair	VPVD	2.55	2.58	2.61	V	-40°C<TA<+105°C; PLS[2:0]=101; edge label not legible	37
PVD threshold, PLS[2:0]=110, first row of pair	VPVD	2.75	2.79	2.82	V	-40°C<TA<+105°C; PLS[2:0]=110; edge label not legible	37
PVD threshold, PLS[2:0]=110, second row of pair	VPVD	2.64	2.67	2.71	V	-40°C<TA<+105°C; PLS[2:0]=110; edge label not legible	37
PVD threshold, PLS[2:0]=111, first row of pair	VPVD	2.84	2.88	2.92	V	-40°C<TA<+105°C; PLS[2:0]=111; edge label not legible	37
PVD threshold, PLS[2:0]=111, second row of pair	VPVD	2.74	2.78	2.81	V	-40°C<TA<+105°C; PLS[2:0]=111; edge label not legible	37
Power-on/power-down reset threshold, first row	VPOR/PDR	1.86	1.88	1.9	V	footnote (1); edge label not legible	37
Power-on/power-down reset threshold, second row	VPOR/PDR	1.91	1.94	1.96	V	footnote (1); edge label not legible	37
PDR hysteresis	VPDRhyst	38.19	55.33	72.47	mV		37
Internal reference voltage	VREFINT	1.2	1.21	1.22	V	VDD=2-3.6 V	38
HSE oscillator frequency	fOSC_IN	4	8	16	MHz		44
HSI accuracy, first row	ACCHSI	-1		1	%	VDD=3.3V; TA range illegible in text	46
HSI accuracy, second row	ACCHSI	-2.76		2.3	%	VDD=3.3V; TA range illegible in text	46
HSI accuracy, third row	ACCHSI	-2.76		2.45	%	VDD=2-3.6V; TA range illegible in text	46
LSI oscillator frequency	fLSI	36.74	41.5	46.26	KHz	VDD=2-3.6 V; TA range illegible in text	46
PLL input frequency	fPLL_IN	1	8	25	MHz		47
PLL output frequency	fPLL_OUT	2		96	MHz	VDD=3.3V; TA range illegible in text	47
Flash programming time	tprog	33.7	37.1	40.5	µs	VDD=2.4~3.6 V; TA range illegible in text	47
Flash mass erase time	tME	25.4	26.5	27.7	ms	VDD=3.3V	47
Flash programming voltage	Vprog	2	3.3	3.6	V	TA range illegible in text	47
Low-level input voltage, TTL port	VIL	-0.5		0.8	V	TTL	50
High-level input voltage, I/O	VIH	2			V	I/O; printed max is VDD+0.5	50
High-level input voltage, FT I/O	VIH	2		5.5	V	FT I/O (5 V tolerant)	50
Low-level input voltage, CMOS port	VIL	-0.5			V	CMOS; printed max is 0.3VDD	50
Weak pull-up resistor	RPU	32	40	49	kΩ	VIN=VSS	50
Weak pull-down resistor	RPD	32	40	49	kΩ	VIN=VDD	50
Output low-level voltage, TTL	VOL			0.4	V	TTL; IIO=+8mA; 2.7V<VDD<3.6V	51
Output high-level voltage, TTL	VOH	2.4			V	8 mA; 2.7V<VDD<3.6V	51
Output low-level voltage, 20 mA port	VOL			1.3	V	IIO=+20mA; 2.7V<VDD<3.6V	51
NRST low-level input voltage	VIL(NRST)	-0.5		0.8	V	VCC=3.3V	53
NRST high-level input voltage	VIH(NRST)	2			V	VCC=3.3V; printed max is VDD+0.5	53
NRST Schmitt trigger hysteresis	Vhys(NRST)	270	300	340	mV	VCC=3.3V	53

CAD (KiCad official)

Symbol: APM32F103RET6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: apm32f103ret6-etched.step / apm32f103ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32f103ret6.step / apm32f103ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Geehy datasheet (75 pp, sha256 6b7b3dc839daa1d7, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# APM32F103RET6

**Geehy** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

APM32F103RET6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and backup registers, specified at 1.8 to 3.6 V. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 with TAMPER-RTC function; output drive is limited (footnote 4: 3 mA, 2 MHz, 30 pF). |
| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14 that serves as the 32.768 kHz LSE oscillator input OSC32_IN, with the same limited drive as PC13. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15 that serves as the 32.768 kHz LSE oscillator output OSC32_OUT, with the same limited drive as PC13. |
| 5 | PD0-OSC_IN | input | High-speed external oscillator input OSC_IN (4 to 16 MHz HSE) on LQFP64; PD0 GPIO is not available on this pin in this package. |
| 6 | PD1-OSC_OUT | output | High-speed external oscillator output OSC_OUT for the 4 to 16 MHz HSE crystal on LQFP64; PD1 GPIO is not available on this pin in this package. |
| 7 | NRST | bidirectional | Active-low reset pin with internal pull-up of 30 to 53 kΩ and about 300 mV Schmitt hysteresis. |
| 8 | PC0 | bidirectional | GPIO PC0 that can be used as ADC123 analog input channel 10 (ADC123_IN10). |
| 9 | PC1 | bidirectional | GPIO PC1 that can be used as ADC123 analog input channel 11 (ADC123_IN11). |
| 10 | PC2 | bidirectional | GPIO PC2 that can be used as ADC123 analog input channel 12 (ADC123_IN12). |
| 11 | PC3 | bidirectional | GPIO PC3 that can be used as ADC123 analog input channel 13 (ADC123_IN13). |
| 12 | VSSA | power_in | Analog ground for the ADC, DAC and analog circuits. |
| 13 | VDDA | power_in | Analog supply, 2.0 to 3.6 V; the ADC and DAC require VDDA of at least 2.4 V. |
| 14 | PA0-WKUP | bidirectional | GPIO PA0 that also provides the WKUP wake-up input, ADC123_IN0, USART2_CTS and timer functions. |
| 15 | PA1 | bidirectional | GPIO PA1 with USART2_RTS, ADC123_IN1, TMR2_CH2 and TMR5_CH2 alternate functions. |
| 16 | PA2 | bidirectional | GPIO PA2 with USART2_TX, ADC123_IN2, TMR5_CH3 and TMR2_CH3 alternate functions. |
| 17 | PA3 | bidirectional | GPIO PA3 with USART2_RX, ADC12_IN3, TMR5_CH4 and TMR2_CH4 alternate functions. |
| 18 | VSS_4 | power_in | Digital ground. |
| 19 | VDD_4 | power_in | Digital supply, 2.0 to 3.6 V. |
| 20 | PA4 | bidirectional | GPIO PA4 with SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4 alternate functions. |
| 21 | PA5 | bidirectional | GPIO PA5 with SPI1_SCK, ADC12_IN5 and DAC_OUT1 alternate functions. |
| 22 | PA6 | bidirectional | GPIO PA6 with SPI1_MISO, ADC12_IN6, TMR8_BKIN, TMR3_CH1 and TMR1_BKIN alternate functions. |
| 23 | PA7 | bidirectional | GPIO PA7 with SPI1_MOSI, ADC12_IN7, TMR8_CH1N, TMR3_CH2 and TMR1_CH1N alternate functions. |
| 24 | PC4 | bidirectional | GPIO PC4 that can be used as ADC12 analog input channel 14 (ADC12_IN14). |
| 25 | PC5 | bidirectional | GPIO PC5 that can be used as ADC12 analog input channel 15 (ADC12_IN15). |
| 26 | PB0 | bidirectional | GPIO PB0 with ADC12_IN8, TMR8_CH2N, TMR3_CH3 and TMR1_CH2N alternate functions. |
| 27 | PB1 | bidirectional | GPIO PB1 with ADC12_IN9, TMR8_CH3N, TMR3_CH4 and TMR1_CH3N alternate functions. |
| 28 | PB2/BOOT1 | bidirectional | 5 V tolerant GPIO PB2 that is also sampled as the BOOT1 boot-mode pin. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO PB10 with I2C2_SCL, I2C4_SCL, USART3_TX and TMR2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO PB11 with I2C2_SDA, I2C4_SDA, USART3_RX and TMR2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Digital ground. |
| 32 | VDD_1 | power_in | Digital supply, 2.0 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO PB12 with SPI2_NSS, I2C2_SMBAI, USART3_CK, I2S2_WS and TMR1_BKIN alternate functions. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO PB13 with SPI2_SCK, I2S2_CK, USART3_CTS and TMR1_CH1N alternate functions. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO PB14 with SPI2_MISO, TMR1_CH2N and USART3_RTS alternate functions. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO PB15 with SPI2_MOSI, I2S2_SD and TMR1_CH3N alternate functions. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO PC6 with I2S2_MCK, TMR8_CH1, SDIO_D6 and TMR3_CH1 alternate functions. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO PC7 with TMR8_CH2, SDIO_D7 and TMR3_CH2 alternate functions. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO PC8 with TMR8_CH3, SDIO_D0 and TMR3_CH3 alternate functions. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO PC9 with TMR8_CH4, SDIO_D1 and TMR3_CH4 alternate functions. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO PA8 with USART1_CK, TMR1_CH1 and MCO alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO PA9 with USART1_TX and TMR1_CH2 alternate functions. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO PA10 with USART1_RX and TMR1_CH3 alternate functions. |
| 44 | PA11 | bidirectional | 5 V tolerant GPIO PA11 with USART1_CTS, USBDDM/USBD2DM, CAN_RX and TMR1_CH4 alternate functions. |
| 45 | PA12 | bidirectional | 5 V tolerant GPIO PA12 with USART1_RTS, USBDDP/USBD2DP, CAN_TX and TMR1_ETR alternate functions. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO PA13 that serves as the JTMS/SWDIO serial-wire debug data pin. |
| 47 | VSS_2 | power_in | Digital ground. |
| 48 | VDD_2 | power_in | Digital supply, 2.0 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO PA14 that serves as the JTCK/SWCLK serial-wire debug clock pin. |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO PA15 with JTDI, SPI3_NSS, TMR2_CH1_ETR and SPI1_NSS alternate functions. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO PC10 with UART4_TX, SDIO_D2 and USART3_TX alternate functions. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO PC11 with UART4_RX, SDIO_D3 and USART3_RX alternate functions. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO PC12 with UART5_TX, SDIO_CK and USART3_CK alternate functions. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO PD2 with TMR3_ETR, UART5_RX and SDIO_CMD alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO PB3 with JTDO, SPI3_SCK, TRACESWO, TMR2_CH2 and SPI1_SCK alternate functions. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO PB4 with NJTRST, SPI3_MISO, TMR3_CH1 and SPI1_MISO alternate functions. |
| 57 | PB5 | bidirectional | GPIO PB5 with I2C1_SMBAI, TIM4_CH1, TMR3_CH2 and SPI1_MOSI alternate functions; not listed as 5 V tolerant. |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO PB6 with I2C1_SCL, I2C3_SCL, TMR4_CH1 and USART1_TX alternate functions. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO PB7 with I2C1_SDA, I2C3_SDA, TMR4_CH2 and USART1_RX alternate functions. |
| 60 | BOOT0 | input | Boot-mode selection input BOOT0, which together with BOOT1 (PB2) selects the boot memory source. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO PB8 with TMR4_CH3, SDIO_D4, I2C1_SCL, I2C3_SCL and CAN_RX alternate functions. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO PB9 with TMR4_CH4, SDIO_D5, I2C1_SDA, I2C3_SDA and CAN_TX alternate functions. |
| 63 | VSS_3 | power_in | Digital ground. |
| 64 | VDD_3 | power_in | Digital supply, 2.0 to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Geehy |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD-VSS (absolute max) | VDD - VSS | -0.3 |  | 4 | V |  | 35 |
| Input voltage on five-volt tolerant pin | VIN | -0.3 |  | 5.5 | V | FT (5V tolerant) pins; printed min is VSS-0.3 | 35 |
| Input voltage on other pins | VIN | -0.3 |  |  | V | printed max is VDD+0.3; printed min is VSS-0.3 | 35 |
| Variation between VDDx and VDD | /VDDx - VDD/ |  |  | 50 | mV |  | 35 |
| Total current into VDD/VDDA power lines | IVDD |  |  | 150 | mA |  | 36 |
| Total current out of VSS ground lines | IVSS |  |  | 150 | mA |  | 36 |
| Output current sunk/sourced by any I/O and control pin | IIO | -25 |  | 25 | mA |  | 36 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 36 |
| Maximum junction temperature (absolute) | TJ |  |  | 150 | °C |  | 36 |
| Internal AHB clock frequency | fHCLK | 0 |  | 96 | MHz |  | 36 |
| APB1 clock frequency | fPCLK1 | 0 |  | 48 | MHz |  | 36 |
| APB2 clock frequency | fPCLK2 | 0 |  | 96 | MHz |  | 36 |
| Supply voltage | VDD | 2 |  | 3.6 | V |  | 36 |
| Analog supply voltage | VDDA | 2 |  | 3.6 | V |  | 37 |
| Analog supply voltage for ADC | VDDA | 2.4 |  | 3.6 | V | ADC used | 37 |
| Backup supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 37 |
| Junction operating temperature | TJ | -40 |  | 150 | °C |  | 37 |
| PVD threshold, PLS[2:0]=000, first row of pair | VPVD | 2.16 | 2.19 | 2.22 | V | -40°C<TA<+105°C; PLS[2:0]=000; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=000, second row of pair | VPVD | 2.06 | 2.09 | 2.11 | V | -40°C<TA<+105°C; PLS[2:0]=000; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=001, first row of pair | VPVD | 2.26 | 2.29 | 2.32 | V | -40°C<TA<+105°C; PLS[2:0]=001; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=001, second row of pair | VPVD | 2.15 | 2.18 | 2.21 | V | -40°C<TA<+105°C; PLS[2:0]=001; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=010, first row of pair | VPVD | 2.36 | 2.39 | 2.42 | V | -40°C<TA<+105°C; PLS[2:0]=010; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=010, second row of pair | VPVD | 2.25 | 2.28 | 2.31 | V | -40°C<TA<+105°C; PLS[2:0]=010; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=011, first row of pair | VPVD | 2.45 | 2.49 | 2.52 | V | -40°C<TA<+105°C; PLS[2:0]=011; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=011, second row of pair | VPVD | 2.35 | 2.38 | 2.41 | V | -40°C<TA<+105°C; PLS[2:0]=011; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=100, first row of pair | VPVD | 2.55 | 2.59 | 2.62 | V | -40°C<TA<+105°C; PLS[2:0]=100; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=100, second row of pair | VPVD | 2.44 | 2.48 | 2.51 | V | -40°C<TA<+105°C; PLS[2:0]=100; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=101, first row of pair | VPVD | 2.65 | 2.68 | 2.72 | V | -40°C<TA<+105°C; PLS[2:0]=101; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=101, second row of pair | VPVD | 2.55 | 2.58 | 2.61 | V | -40°C<TA<+105°C; PLS[2:0]=101; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=110, first row of pair | VPVD | 2.75 | 2.79 | 2.82 | V | -40°C<TA<+105°C; PLS[2:0]=110; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=110, second row of pair | VPVD | 2.64 | 2.67 | 2.71 | V | -40°C<TA<+105°C; PLS[2:0]=110; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=111, first row of pair | VPVD | 2.84 | 2.88 | 2.92 | V | -40°C<TA<+105°C; PLS[2:0]=111; edge label not legible | 37 |
| PVD threshold, PLS[2:0]=111, second row of pair | VPVD | 2.74 | 2.78 | 2.81 | V | -40°C<TA<+105°C; PLS[2:0]=111; edge label not legible | 37 |
| Power-on/power-down reset threshold, first row | VPOR/PDR | 1.86 | 1.88 | 1.9 | V | footnote (1); edge label not legible | 37 |
| Power-on/power-down reset threshold, second row | VPOR/PDR | 1.91 | 1.94 | 1.96 | V | footnote (1); edge label not legible | 37 |
| PDR hysteresis | VPDRhyst | 38.19 | 55.33 | 72.47 | mV |  | 37 |
| Internal reference voltage | VREFINT | 1.2 | 1.21 | 1.22 | V | VDD=2-3.6 V | 38 |
| HSE oscillator frequency | fOSC_IN | 4 | 8 | 16 | MHz |  | 44 |
| HSI accuracy, first row | ACCHSI | -1 |  | 1 | % | VDD=3.3V; TA range illegible in text | 46 |
| HSI accuracy, second row | ACCHSI | -2.76 |  | 2.3 | % | VDD=3.3V; TA range illegible in text | 46 |
| HSI accuracy, third row | ACCHSI | -2.76 |  | 2.45 | % | VDD=2-3.6V; TA range illegible in text | 46 |
| LSI oscillator frequency | fLSI | 36.74 | 41.5 | 46.26 | KHz | VDD=2-3.6 V; TA range illegible in text | 46 |
| PLL input frequency | fPLL_IN | 1 | 8 | 25 | MHz |  | 47 |
| PLL output frequency | fPLL_OUT | 2 |  | 96 | MHz | VDD=3.3V; TA range illegible in text | 47 |
| Flash programming time | tprog | 33.7 | 37.1 | 40.5 | µs | VDD=2.4~3.6 V; TA range illegible in text | 47 |
| Flash mass erase time | tME | 25.4 | 26.5 | 27.7 | ms | VDD=3.3V | 47 |
| Flash programming voltage | Vprog | 2 | 3.3 | 3.6 | V | TA range illegible in text | 47 |
| Low-level input voltage, TTL port | VIL | -0.5 |  | 0.8 | V | TTL | 50 |
| High-level input voltage, I/O | VIH | 2 |  |  | V | I/O; printed max is VDD+0.5 | 50 |
| High-level input voltage, FT I/O | VIH | 2 |  | 5.5 | V | FT I/O (5 V tolerant) | 50 |
| Low-level input voltage, CMOS port | VIL | -0.5 |  |  | V | CMOS; printed max is 0.3VDD | 50 |
| Weak pull-up resistor | RPU | 32 | 40 | 49 | kΩ | VIN=VSS | 50 |
| Weak pull-down resistor | RPD | 32 | 40 | 49 | kΩ | VIN=VDD | 50 |
| Output low-level voltage, TTL | VOL |  |  | 0.4 | V | TTL; IIO=+8mA; 2.7V<VDD<3.6V | 51 |
| Output high-level voltage, TTL | VOH | 2.4 |  |  | V | 8 mA; 2.7V<VDD<3.6V | 51 |
| Output low-level voltage, 20 mA port | VOL |  |  | 1.3 | V | IIO=+20mA; 2.7V<VDD<3.6V | 51 |
| NRST low-level input voltage | VIL(NRST) | -0.5 |  | 0.8 | V | VCC=3.3V | 53 |
| NRST high-level input voltage | VIH(NRST) | 2 |  |  | V | VCC=3.3V; printed max is VDD+0.5 | 53 |
| NRST Schmitt trigger hysteresis | Vhys(NRST) | 270 | 300 | 340 | mV | VCC=3.3V | 53 |

## CAD (KiCad official)

- Symbol: `APM32F103RET6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `apm32f103ret6-etched.step` / `apm32f103ret6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `apm32f103ret6.step` / `apm32f103ret6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Geehy datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893324174770176) (75 pp, sha256 `6b7b3dc839daa1d7`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/apm32f103ret6-datasheet.pdf)