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APM32F051R8T6

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Geehy Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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APM32F051R8T6

Geehy · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

APM32F051R8T6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for the RTC, the external 32 kHz oscillator and backup registers when VDD is off, specified at 1.65 to 3.6 V.
2 PC13 bidirectional I/O powered through the power switch, sinking at most 3 mA, limited to 2 MHz at 30 pF in output mode, with RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2 functions.
3 PC14-OSC32_IN bidirectional I/O powered through the power switch with a 3 mA sink limit, used as OSC32_IN for the external 32.768 kHz oscillator.
4 PC15-OSC32_OUT bidirectional I/O powered through the power switch with a 3 mA sink limit, used as OSC32_OUT for the external 32.768 kHz oscillator.
5 PF0-OSC_IN bidirectional 5 V tolerant I/O (FT) that serves as OSC_IN for the 4 to 32 MHz external high-speed clock.
6 PF1-OSC_OUT bidirectional 5 V tolerant I/O (FT) that serves as OSC_OUT for the 4 to 32 MHz external high-speed clock.
7 NRST bidirectional Active-low reset input and internal reset output with a permanent internal pull-up of 30 to 50 kΩ (40 kΩ typical).
8 PC0 bidirectional 3.3 V standard analog-capable I/O (TTa) that can be used as ADC_IN10 or EVENTOUT.
9 PC1 bidirectional 3.3 V standard analog-capable I/O (TTa) that can be used as ADC_IN11 or EVENTOUT.
10 PC2 bidirectional 3.3 V standard analog-capable I/O (TTa) that can be used as ADC_IN12 or EVENTOUT.
11 PC3 bidirectional 3.3 V standard analog-capable I/O (TTa) that can be used as ADC_IN13 or EVENTOUT.
12 VSSA power_in Analog ground for the ADC, DAC, reset and RC oscillator blocks, referenced to VSS.
13 VDDA power_in Analog supply for the ADC, DAC, reset, RC oscillators and PLL, which must always be greater than or equal to VDD and is 2.4 to 3.6 V when ADC or DAC is used.
14 PA0 bidirectional 3.3 V standard analog-capable I/O (TTa) with USART2_CTS, TMR2_CH1_ETR, COMP1_OUT, TSC_G1_IO1 and ADC_IN0 functions.
15 PA1 bidirectional 3.3 V standard analog-capable I/O (TTa) with USART2_RTS, TMR2_CH2, TSC_G1_IO2, EVENTOUT and ADC_IN1 functions.
16 PA2 bidirectional 3.3 V standard analog-capable I/O (TTa) with USART2_TX, TMR2_CH3, TMR15_CH1, COMP2_OUT and ADC_IN2 functions.
17 PA3 bidirectional 3.3 V standard analog-capable I/O (TTa) with USART2_RX, TMR2_CH4, TMR15_CH2 and ADC_IN3 functions.
18 PF4 bidirectional 5 V tolerant I/O (FT) with an EVENTOUT alternate function.
19 PF5 bidirectional 5 V tolerant I/O (FT) with an EVENTOUT alternate function.
20 PA4 bidirectional 3.3 V standard analog-capable I/O (TTa) with SPI1_NSS, I2S1_WS, USART2_CK, TMR14_CH1, ADC_IN4, COMP1_INM4 and DAC_OUT1 functions.
21 PA5 bidirectional 3.3 V standard analog-capable I/O (TTa) with SPI1_SCK, I2S1_CK, CEC, TMR2_CH1_ETR and ADC_IN5 functions.
22 PA6 bidirectional 3.3 V standard analog-capable I/O (TTa) with SPI1_MISO, I2S1_MCK, TMR3_CH1, TMR1_BKIN, COMP1_OUT and ADC_IN6 functions.
23 PA7 bidirectional 3.3 V standard analog-capable I/O (TTa) with SPI1_MOSI, I2S1_SD, TMR3_CH2, COMP2_OUT and ADC_IN7 functions.
24 PC4 bidirectional 3.3 V standard analog-capable I/O (TTa) with EVENTOUT and ADC_IN14 functions.
25 PC5 bidirectional 3.3 V standard analog-capable I/O (TTa) with TSC_G3_IO1 and ADC_IN15 functions.
26 PB0 bidirectional 3.3 V standard analog-capable I/O (TTa) with TMR3_CH3, TMR1_CH2N, TSC_G3_IO2, EVENTOUT and ADC_IN8 functions.
27 PB1 bidirectional 3.3 V standard analog-capable I/O (TTa) with TMR3_CH4, TMR14_CH1, TMR1_CH3N, TSC_G3_IO3 and ADC_IN9 functions.
28 PB2 bidirectional 5 V tolerant I/O (FT) with a TSC_G3_IO4 touch-sensing function.
29 PB10 bidirectional 5 V tolerant I/O (FT) with I2C2_SCL, CEC, TMR2_CH3 and TSC_SYNC functions.
30 PB11 bidirectional 5 V tolerant I/O (FT) with I2C2_SDA, TMR2_CH4, TSC_G6_IO1 and EVENTOUT functions.
31 VSS power_in Ground pin for the digital supply, referenced to 0 V.
32 VDD power_in Digital supply and I/O supply, specified at 2.0 to 3.6 V.
33 PB12 bidirectional 5 V tolerant I/O (FT) with SPI2_NSS, TMR1_BKIN, TSC_G6_IO2 and EVENTOUT functions.
34 PB13 bidirectional 5 V tolerant I/O (FT) with SPI2_SCK, TMR1_CH1N and TSC_G6_IO3 functions.
35 PB14 bidirectional 5 V tolerant I/O (FT) with SPI2_MISO, TMR15_CH1, TMR1_CH2N and TSC_G6_IO4 functions.
36 PB15 bidirectional 5 V tolerant I/O (FT) with SPI2_MOSI, TMR15_CH2, TMR1_CH3N and RTC_REFIN functions.
37 PC6 bidirectional 5 V tolerant I/O (FT) with a TMR3_CH1 alternate function.
38 PC7 bidirectional 5 V tolerant I/O (FT) with a TMR3_CH2 alternate function.
39 PC8 bidirectional 5 V tolerant I/O (FT) with a TMR3_CH3 alternate function.
40 PC9 bidirectional 5 V tolerant I/O (FT) with a TMR3_CH4 alternate function.
41 PA8 bidirectional 5 V tolerant I/O (FT) with USART1_CK, TMR1_CH1, EVENTOUT and MCO functions.
42 PA9 bidirectional 5 V tolerant I/O (FT) with USART1_TX, TMR1_CH2, TMR15_BKIN and TSC_G4_IO1 functions.
43 PA10 bidirectional 5 V tolerant I/O (FT) with USART1_RX, TMR1_CH3, TMR17_BKIN and TSC_G4_IO2 functions.
44 PA11 bidirectional 5 V tolerant I/O (FT) with USART1_CTS, TMR1_CH4, COMP1_OUT, TSC_G4_IO3 and EVENTOUT functions.
45 PA12 bidirectional 5 V tolerant I/O (FT) with USART1_RTS, TMR1_ETR, COMP2_OUT, TSC_G4_IO4 and EVENTOUT functions.
46 PA13 bidirectional 5 V tolerant I/O (FT) that is the SWDIO debug data line after reset, with an internal pull-up enabled, and also provides IR_OUT.
47 PF6 bidirectional 5 V tolerant I/O (FT) with an I2C2_SCL alternate function.
48 PF7 bidirectional 5 V tolerant I/O (FT) with an I2C2_SDA alternate function.
49 PA14 bidirectional 5 V tolerant I/O (FT) that is the SWCLK debug clock after reset, with an internal pull-down enabled, and also provides USART2_TX.
50 PA15 bidirectional 5 V tolerant I/O (FT) with SPI1_NSS, I2S1_WS, USART2_RX, TMR2_CH1_ETR and EVENTOUT functions.
51 PC10 bidirectional 5 V tolerant general-purpose I/O (FT) with no alternate function listed for this pin in the pin table.
52 PC11 bidirectional 5 V tolerant general-purpose I/O (FT) with no alternate function listed for this pin in the pin table.
53 PC12 bidirectional 5 V tolerant general-purpose I/O (FT) with no alternate function listed for this pin in the pin table.
54 PD2 bidirectional 5 V tolerant I/O (FT) with a TMR3_ETR alternate function.
55 PB3 bidirectional 5 V tolerant I/O (FT) with SPI1_SCK, I2S1_CK, TMR2_CH2, TSC_G5_IO1 and EVENTOUT functions.
56 PB4 bidirectional 5 V tolerant I/O (FT) with SPI1_MISO, I2S1_MCK, TMR3_CH1, TSC_G5_IO2 and EVENTOUT functions.
57 PB5 bidirectional 5 V tolerant I/O (FT) with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TMR16_BKIN and TMR3_CH2 functions.
58 PB6 bidirectional 5 V tolerant I/O with FM+ (up to 1 Mbit/s I2C) capability (FTf), with I2C1_SCL, USART1_TX, TMR16_CH1N and TSC_G5_IO3 functions.
59 PB7 bidirectional 5 V tolerant I/O with FM+ (up to 1 Mbit/s I2C) capability (FTf), with I2C1_SDA, USART1_RX, TMR17_CH1N and TSC_G5_IO4 functions.
60 BOOT0 input Dedicated boot selection pin that sets the startup mode, with an input voltage range of 0 to 5.5 V.
61 PB8 bidirectional 5 V tolerant I/O with FM+ capability (FTf), with I2C1_SCL, CEC, TMR16_CH1 and TSC_SYNC functions.
62 PB9 bidirectional 5 V tolerant I/O with FM+ capability (FTf), with I2C1_SDA, IR_OUT, TMR17_CH1 and EVENTOUT functions.
63 VSS power_in Ground pin for the digital supply, referenced to 0 V.
64 VDD power_in Digital supply and I/O supply, specified at 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer Geehy
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: APM32F051R8T6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: apm32f051r8t6-etched.step / apm32f051r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32f051r8t6.step / apm32f051r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Geehy datasheet (72 pp, sha256 9c2075b63f284fd7, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF