component
APM32F051K8T6
Public Made by Adomby adom
Geehy Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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APM32F051K8T6
Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
APM32F051K8T6 from Geehy, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Digital and I/O supply, 2.0 V to 3.6 V; VDD also powers the core circuits through the voltage regulator. |
| 2 | PF0-OSC_IN | bidirectional | 5 V tolerant (FT) general-purpose I/O PF0, also the 4-32 MHz external crystal oscillator input OSC_IN. |
| 3 | PF1-OSC_OUT | bidirectional | 5 V tolerant (FT) general-purpose I/O PF1, also the 4-32 MHz external crystal oscillator output OSC_OUT. |
| 4 | NRST | bidirectional | Active-low reset pin with an internal weak pull-up of 30-50 kΩ; it also serves as an internal reset output. |
| 5 | VDDA | power_in | Analog supply for the ADC, DAC, reset block, RC oscillators and PLL; it must always be greater than or equal to VDD and is 2.4 V to 3.6 V when the ADC or DAC is used. |
| 6 | PA0 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN0; alternate functions include USART2_CTS, TMR2_CH1_ETR, COMP1_OUT and TSC_G1_IO1. |
| 7 | PA1 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN1; alternate functions include USART2_RTS, TMR2_CH2, TSC_G1_IO2 and EVENTOUT. |
| 8 | PA2 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN2; alternate functions include USART2_TX, TMR2_CH3, TMR15_CH1, COMP2_OUT and TSC_G1_IO3. |
| 9 | PA3 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN3; alternate functions include USART2_RX, TMR2_CH4, TMR15_CH2 and TSC_G1_IO4. |
| 10 | PA4 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN4 and DAC_OUT1; alternate functions include SPI1_NSS/I2S1_WS, USART2_CK and TMR14_CH1. |
| 11 | PA5 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN5; alternate functions include SPI1_SCK/I2S1_CK, CEC and TMR2_CH1_ETR. |
| 12 | PA6 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN6; alternate functions include SPI1_MISO/I2S1_MCK, TMR3_CH1, TMR1_BKIN and COMP1_OUT. |
| 13 | PA7 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN7; alternate functions include SPI1_MOSI/I2S1_SD, TMR3_CH2, TMR1_CH1N and COMP2_OUT. |
| 14 | PB0 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN8; alternate functions include TMR3_CH3, TMR1_CH2N, TSC_G3_IO2 and EVENTOUT. |
| 15 | PB1 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN9; alternate functions include TMR3_CH4, TMR14_CH1, TMR1_CH3N and TSC_G3_IO3. |
| 16 | VSS | power_in | Ground reference (0 V) for digital circuits and I/O; all voltages are referenced to VSS. |
| 17 | VDD | power_in | Digital and I/O supply, 2.0 V to 3.6 V; VDD also powers the core circuits through the voltage regulator. |
| 18 | PA8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include MCO, USART1_CK, TMR1_CH1 and EVENTOUT. |
| 19 | PA9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_TX, TMR1_CH2, TMR15_BKIN and TSC_G4_IO1. |
| 20 | PA10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_RX, TMR1_CH3, TMR17_BKIN and TSC_G4_IO2. |
| 21 | PA11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_CTS, TMR1_CH4, COMP1_OUT and EVENTOUT. |
| 22 | PA12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_RTS, TMR1_ETR, COMP2_OUT and EVENTOUT. |
| 23 | PA13 | bidirectional | 5 V tolerant (FT) I/O; after reset it is the SWDIO serial-wire debug data pin, with alternate function IR_OUT. |
| 24 | PA14 | bidirectional | 5 V tolerant (FT) I/O; after reset it is the SWCLK serial-wire debug clock pin, with alternate function USART2_TX. |
| 25 | PA15 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_NSS/I2S1_WS, USART2_RX, TMR2_CH1_ETR and EVENTOUT. |
| 26 | PB3 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_SCK/I2S1_CK, TMR2_CH2, TSC_G5_IO1 and EVENTOUT. |
| 27 | PB4 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_MISO/I2S1_MCK, TMR3_CH1, TSC_G5_IO2 and EVENTOUT. |
| 28 | PB5 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_MOSI/I2S1_SD, I2C1_SMBA, TMR16_BKIN and TMR3_CH2. |
| 29 | PB6 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf) for fast-mode-plus I2C up to 1 Mbit/s; alternate functions include I2C1_SCL, USART1_TX, TMR16_CH1N and TSC_G5_IO3. |
| 30 | PB7 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf) for fast-mode-plus I2C up to 1 Mbit/s; alternate functions include I2C1_SDA, USART1_RX, TMR17_CH1N and TSC_G5_IO4. |
| 31 | BOOT0 | input | Dedicated boot-select pin (B) sampled at start-up to choose user Flash, system memory or embedded SRAM boot; input range 0 to 5.5 V. |
| 32 | VSS | power_in | Ground reference (0 V) for digital circuits and I/O; all voltages are referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Geehy |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
APM32F051K8T6 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
apm32f051k8t6-etched.step/apm32f051k8t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apm32f051k8t6.step/apm32f051k8t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Geehy datasheet (72 pp, sha256
4c3e595c7482399e, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# APM32F051K8T6
**Geehy** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
APM32F051K8T6 from Geehy, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Digital and I/O supply, 2.0 V to 3.6 V; VDD also powers the core circuits through the voltage regulator. |
| 2 | PF0-OSC_IN | bidirectional | 5 V tolerant (FT) general-purpose I/O PF0, also the 4-32 MHz external crystal oscillator input OSC_IN. |
| 3 | PF1-OSC_OUT | bidirectional | 5 V tolerant (FT) general-purpose I/O PF1, also the 4-32 MHz external crystal oscillator output OSC_OUT. |
| 4 | NRST | bidirectional | Active-low reset pin with an internal weak pull-up of 30-50 kΩ; it also serves as an internal reset output. |
| 5 | VDDA | power_in | Analog supply for the ADC, DAC, reset block, RC oscillators and PLL; it must always be greater than or equal to VDD and is 2.4 V to 3.6 V when the ADC or DAC is used. |
| 6 | PA0 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN0; alternate functions include USART2_CTS, TMR2_CH1_ETR, COMP1_OUT and TSC_G1_IO1. |
| 7 | PA1 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN1; alternate functions include USART2_RTS, TMR2_CH2, TSC_G1_IO2 and EVENTOUT. |
| 8 | PA2 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN2; alternate functions include USART2_TX, TMR2_CH3, TMR15_CH1, COMP2_OUT and TSC_G1_IO3. |
| 9 | PA3 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN3; alternate functions include USART2_RX, TMR2_CH4, TMR15_CH2 and TSC_G1_IO4. |
| 10 | PA4 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN4 and DAC_OUT1; alternate functions include SPI1_NSS/I2S1_WS, USART2_CK and TMR14_CH1. |
| 11 | PA5 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN5; alternate functions include SPI1_SCK/I2S1_CK, CEC and TMR2_CH1_ETR. |
| 12 | PA6 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN6; alternate functions include SPI1_MISO/I2S1_MCK, TMR3_CH1, TMR1_BKIN and COMP1_OUT. |
| 13 | PA7 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN7; alternate functions include SPI1_MOSI/I2S1_SD, TMR3_CH2, TMR1_CH1N and COMP2_OUT. |
| 14 | PB0 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN8; alternate functions include TMR3_CH3, TMR1_CH2N, TSC_G3_IO2 and EVENTOUT. |
| 15 | PB1 | bidirectional | 3.3 V standard I/O (TTa) connected to ADC_IN9; alternate functions include TMR3_CH4, TMR14_CH1, TMR1_CH3N and TSC_G3_IO3. |
| 16 | VSS | power_in | Ground reference (0 V) for digital circuits and I/O; all voltages are referenced to VSS. |
| 17 | VDD | power_in | Digital and I/O supply, 2.0 V to 3.6 V; VDD also powers the core circuits through the voltage regulator. |
| 18 | PA8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include MCO, USART1_CK, TMR1_CH1 and EVENTOUT. |
| 19 | PA9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_TX, TMR1_CH2, TMR15_BKIN and TSC_G4_IO1. |
| 20 | PA10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_RX, TMR1_CH3, TMR17_BKIN and TSC_G4_IO2. |
| 21 | PA11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_CTS, TMR1_CH4, COMP1_OUT and EVENTOUT. |
| 22 | PA12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include USART1_RTS, TMR1_ETR, COMP2_OUT and EVENTOUT. |
| 23 | PA13 | bidirectional | 5 V tolerant (FT) I/O; after reset it is the SWDIO serial-wire debug data pin, with alternate function IR_OUT. |
| 24 | PA14 | bidirectional | 5 V tolerant (FT) I/O; after reset it is the SWCLK serial-wire debug clock pin, with alternate function USART2_TX. |
| 25 | PA15 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_NSS/I2S1_WS, USART2_RX, TMR2_CH1_ETR and EVENTOUT. |
| 26 | PB3 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_SCK/I2S1_CK, TMR2_CH2, TSC_G5_IO1 and EVENTOUT. |
| 27 | PB4 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_MISO/I2S1_MCK, TMR3_CH1, TSC_G5_IO2 and EVENTOUT. |
| 28 | PB5 | bidirectional | 5 V tolerant (FT) I/O; alternate functions include SPI1_MOSI/I2S1_SD, I2C1_SMBA, TMR16_BKIN and TMR3_CH2. |
| 29 | PB6 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf) for fast-mode-plus I2C up to 1 Mbit/s; alternate functions include I2C1_SCL, USART1_TX, TMR16_CH1N and TSC_G5_IO3. |
| 30 | PB7 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf) for fast-mode-plus I2C up to 1 Mbit/s; alternate functions include I2C1_SDA, USART1_RX, TMR17_CH1N and TSC_G5_IO4. |
| 31 | BOOT0 | input | Dedicated boot-select pin (B) sampled at start-up to choose user Flash, system memory or embedded SRAM boot; input range 0 to 5.5 V. |
| 32 | VSS | power_in | Ground reference (0 V) for digital circuits and I/O; all voltages are referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Geehy |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
## CAD (KiCad official)
- Symbol: `APM32F051K8T6`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `apm32f051k8t6-etched.step` / `apm32f051k8t6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `apm32f051k8t6.step` / `apm32f051k8t6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Geehy datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943506538156032) (72 pp, sha256 `4c3e595c7482399e`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/apm32f051k8t6-datasheet.pdf)