component
APM32F003F6P6
Public Made by Adomby adom
Geehy Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
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| viewers | 18d ago |
| apm32f003f6p6-etched.glb | 18d ago |
| apm32f003f6p6-etched.step | 18d ago |
| apm32f003f6p6-hero.glb | 18d ago |
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| apm32f003f6p6.step | 18d ago |
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| README.md | 18d ago |
APM32F003F6P6
Geehy · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
APM32F003F6P6 from Geehy, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD4 | bidirectional | General-purpose I/O PD4 (floating after reset, high-sink capable, external interrupt capable) that can be remapped to BUZZER, TMR2_CH1, USART1_CK or TMR1A_CH2. |
| 2 | PD5 | bidirectional | General-purpose I/O PD5 (high-sink capable, external interrupt capable) with analog inputs AIN5 and VAIN2, USART1_TX, TMR1A_CH3 and TMR1A_CH1N alternate functions. |
| 3 | PD6 | bidirectional | General-purpose I/O PD6 (high-sink capable, external interrupt capable) with analog inputs AIN6 and VAIP2, USART1_RX, TMR1A_CH4 and TMR1A_CH2N alternate functions. |
| 4 | NRST | bidirectional | Active-low reset pin with CMOS input, internal pull-up RPU of 30-60-80 kΩ, VIL max 0.3×VDD and VIH min 0.7×VDD, and output low level VOL max 0.5 V at IOL = 2 mA. |
| 5 | PA1 | bidirectional | I/O PA1 that serves as the OSCIN oscillator input for the HSECLK crystal/external clock; it does not support wake-up from Halt or Active-Halt modes. |
| 6 | PA2 | bidirectional | I/O PA2 that serves as the OSCOUT oscillator output for the HSECLK crystal. |
| 7 | VSS | power_in | Ground reference for the device; all voltage parameters are referenced to VSS and VSS-to-VSS pin differences must stay within 50 mV. |
| 8 | VCAP | power_out | Output of the internal 1.5 V core regulator that requires an external capacitor between 470 nF and 3300 nF to VSS. |
| 9 | VDD | power_in | Main supply pin, 2.0 V to 5.5 V (absolute maximum VDD-VSS 6.5 V range per datasheet ratings), which also powers the internal voltage regulators and the analog supply VDDA. |
| 10 | PA3 | bidirectional | General-purpose I/O PA3 (high-sink capable, external interrupt capable) with TMR2_CH3, TMR1_ETR, USART3_CK and SPI_NSS alternate functions. |
| 11 | PB5 | bidirectional | True open-drain I/O PB5 (external interrupt capable) with I2C_SDA, USART3_RX and TMR1_BKIN alternate functions. |
| 12 | PB4 | bidirectional | True open-drain I/O PB4 (external interrupt capable) with I2C_SCL, USART3_TX and ADC_ETR alternate functions. |
| 13 | PC3 | bidirectional | General-purpose I/O PC3 (high-sink capable, external interrupt capable) with TMR1_CH3, analog inputs AIN7 and VAIN3, TLI and TMR1_CH1N alternate functions. |
| 14 | PC4 | bidirectional | General-purpose I/O PC4 (high-sink capable, external interrupt capable) with TMR1_CH4, CLK_CCO, analog inputs AIN2 and VAIP1, and TMR1_CH2N alternate functions. |
| 15 | PC5 | bidirectional | General-purpose I/O PC5 (high-sink capable, external interrupt capable) with SPI_SCK, analog inputs AIN0 and VAIP0, and TMR2_CH1 alternate functions. |
| 16 | PC6 | bidirectional | General-purpose I/O PC6 (high-sink capable, external interrupt capable) with SPI_MOSI, analog inputs AIN1 and VAIN0, and TMR1_CH1 alternate functions. |
| 17 | PC7 | bidirectional | General-purpose I/O PC7 (high-sink capable, external interrupt capable) with SPI_MISO and TMR1_CH2 alternate functions. |
| 18 | PD1 | bidirectional | General-purpose I/O PD1 (high-sink capable, external interrupt capable) that is also the SWD debug pin, with USART2_CK and TMR1A_CH1 alternate functions; its speed class is O4 (starts at high speed). |
| 19 | PD2 | bidirectional | General-purpose I/O PD2 (high-sink capable, external interrupt capable) that is also the SWCLK debug pin, with analog inputs AIN3 and VAIN1, USART2_RX, TMR1A_BKIN and TMR2_CH3 alternate functions. |
| 20 | PD3 | bidirectional | General-purpose I/O PD3 (high-sink capable, external interrupt capable) with analog input AIN4 and VAIP3, TMR2_CH2, ADC_ETR, USART2_TX and TMR1A_ETR alternate functions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Geehy |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
APM32F003F6P6 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
apm32f003f6p6-etched.step/apm32f003f6p6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apm32f003f6p6.step/apm32f003f6p6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Geehy datasheet (50 pp, sha256
cfda07eeb571ed05, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).