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APM32E103RCT6

Public Made by Adom

by adom

Geehy Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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APM32E103RCT6

Geehy · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

APM32E103RCT6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain power supply; the VBAT range of the backup domain power supply is 1.8 V to 3.6 V.
2 PC13-TAMPER-RTC bidirectional I/O pin with 3.3 V standard (STD) structure; default function is TAMPER_RTC.
3 PC14-OSC32_IN bidirectional I/O pin with 3.3 V standard (STD) structure; default function is OSC32_IN.
4 PC15-OSC32_OUT bidirectional I/O pin with 3.3 V standard (STD) structure; default function is OSC32_OUT.
5 PD0-OSC_IN bidirectional Port pin named with the OSC_IN function; its structure and default function are in Table 3 rows not included in this excerpt.
6 PD1-OSC_OUT bidirectional Port pin named with the OSC_OUT function; its structure and default function are in Table 3 rows not included in this excerpt.
7 NRST bidirectional Bidirectional reset pin with a built-in pull-up resistor (RST structure).
8 PC0 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
9 PC1 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
10 PC2 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
11 PC3 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
12 VSSA power_in Analog ground reference.
13 VDDA power_in Analog supply; the VDDA range is 2.0 V to 3.6 V.
14 PA0-WKUP bidirectional General-purpose I/O port pin with the WKUP wake-up function per its pin name; structure is in Table 3 rows not included in this excerpt.
15 PA1 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
16 PA2 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
17 PA3 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
18 VSS_4 power_in Digital ground reference.
19 VDD_4 power_in Digital supply; the VDD range is 2.0 V to 3.6 V.
20 PA4 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
21 PA5 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
22 PA6 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
23 PA7 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
24 PC4 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
25 PC5 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
26 PB0 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
27 PB1 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
28 PB2 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
29 PB10 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
30 PB11 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
31 VSS_1 power_in Digital ground reference.
32 VDD_1 power_in Digital supply; the VDD range is 2.0 V to 3.6 V.
33 PB12 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
34 PB13 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
35 PB14 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
36 PB15 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
37 PC6 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
38 PC7 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
39 PC8 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
40 PC9 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
41 PA8 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
42 PA9 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
43 PA10 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
44 PA11 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
45 PA12 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
46 PA13 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
47 VSS_2 power_in Digital ground reference.
48 VDD_2 power_in Digital supply; the VDD range is 2.0 V to 3.6 V.
49 PA14 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
50 PA15 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
51 PC10 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
52 PC11 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
53 PC12 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
54 PD2 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
55 PB3 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
56 PB4 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
57 PB5 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
58 PB6 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
59 PB7 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
60 BOOT0 input Dedicated Boot0 pin (B structure per Table 2 legend).
61 PB8 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
62 PB9 bidirectional General-purpose I/O port pin; its structure and default/remap functions are in Table 3 rows not included in this excerpt.
63 VSS_3 power_in Digital ground reference.
64 VDD_3 power_in Digital supply; the VDD range is 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Geehy
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal AHB clock frequency fHCLK 120 MHz 34
Internal APB1 clock frequency fPCLK1 60 MHz 34
Internal APB2 clock frequency fPCLK2 120 MHz 34
Main power supply voltage VDD 2 3.6 V 34
Analog power supply voltage (neither ADC nor DAC used) VDDA 3.6 V When neither ADC nor DAC is used; must be the same as VDD 34
Analog power supply voltage (ADC and DAC used) VDDA 2.4 3.6 V When ADC and DAC are used 34
Power supply voltage of backup domain VBAT 1.8 3.6 V 34
Ambient temperature (temperature number 6) TA -40 85 ℃ Temperature number 6; maximum power dissipation 34
Storage temperature range TSTG -55 150 ℃ 35
Maximum junction temperature TJ 150 ℃ 35
External main power supply voltage VDD-VSS -0.3 4 V 35
External analog power supply voltage VDDA-VSSA -0.3 4 V 35
Power supply voltage of external backup domain VBAT-VSS -0.3 4 V 35
Voltage difference allowed by VDD>VDDA VDD-VDDA 0.3 V VDD>VDDA 35
Input voltage on FT pins VIN 5.5 V Input voltage on FT pins 35
Voltage difference between different power supply pins /ΔVDDx/ 50 mV 35
Voltage difference between different grounding pins /VSSx-VSS/ 50 mV 35
Total current into VDD/VDDA power lines (source) IVDD 150 mA 35
Total current out of VSS ground lines (sink) IVSS 150 mA 35
Sink current on any I/O and control pins (printed 'Irrigation current') IIO 25 mA 35
Source current on any I/O and control pins IIO -25 mA Source current (printed as -25) 35
Injection current of 5T pin (as printed) IINJ(PIN) -5 mA Injection current of 5T pin (as printed) 35
Injection current of other pins IINJ(PIN) -5 5 mA Injection current of other pins 35
Total injection current on all I/O and control pins ΣIINJ(PIN) -25 25 mA 35
ESD voltage (human body model) VESD(HBM) -5000 5000 V TA = +25 ℃ 36
16-bit programming time tprog 40 46.08 70 μs TA = -40105℃, VDD=2.43.6V 36
Page (2KBytes) erase time tERASE 10 30 ms TA = -40105℃, VDD=2.43.6V 36
Programming voltage Vprog 2 3.6 V TA = -40~105℃ 36
HSECLK oscillator frequency fOSC_IN 4 8 16 MHz 37
HSECLK current consumption IDD(HSECLK) 0.56 mA VDD=3.3V, CL=10pF@8MHz 37
LSECLK current consumption IDD(LSECLK) 0.8 μA 37
Accuracy of HSICLK oscillator (factory calibration) ACCHSICLK -1 1 % Factory calibration; VDD=3.3V, TA=25℃ 37
Accuracy of HSICLK oscillator ACCHSICLK -1.4 1.15 % VDD=2-3.6V, TA=-40~105℃ 37
Power consumption of HSICLK oscillator IDDA(HSICLK) 76 μA 37
LSICLK oscillator frequency fLSICLK 36 40 51 KHz VDD=2-3.6V, TA=-40~105℃ 38
Power consumption of LSICLK oscillator IDD(LSICLK) 0.56 μA 38
PLL input clock fPLL_IN 1 8 25 MHz 38
PLL input clock duty cycle 40 60 % 38
PLL frequency doubling output clock fPLL_OUT 16 120 MHz VDD=3.3V, TA=-40~105℃ 38
PLL phase locking time tLOCK 200 μs 38
Power-on/power-down reset threshold VPOR/PDR 1.84 1.86 1.88 V Falling edge 38
Power-on/power-down reset threshold VPOR/PDR 1.9 1.92 1.93 V Rising edge 38
PDR hysteresis VPDRhyst 50 54 60 mV 38
Reset duration TRSTTEMPO 0.9 1.39 4.9 ms 38
Programmable power supply voltage detector VPVD 2.17 2.2 V PLS[2:0]=000 (rising edge) 38
Programmable power supply voltage detector VPVD 2.06 2.1 V PLS[2:0]=000 (falling edge) 38
Programmable power supply voltage detector VPVD 2.27 2.3 V PLS[2:0]=001 (rising edge) 38
Programmable power supply voltage detector VPVD 2.16 2.19 V PLS[2:0]=001 (falling edge) 39
Programmable power supply voltage detector VPVD 2.37 2.4 V PLS[2:0]=010 (rising edge) 39
Programmable power supply voltage detector VPVD 2.26 2.29 V PLS[2:0]=010 (falling edge) 39
Programmable power supply voltage detector VPVD 2.46 2.5 V PLS[2:0]=011 (rising edge) 39
Programmable power supply voltage detector VPVD 2.36 2.39 V PLS[2:0]=011 (falling edge) 39
Programmable power supply voltage detector VPVD 2.57 2.6 V PLS[2:0]=100 (rising edge) 39
Programmable power supply voltage detector VPVD 2.45 2.49 V PLS[2:0]=100 (falling edge) 39
Programmable power supply voltage detector VPVD 2.66 2.7 V PLS[2:0]=101 (rising edge) 39
Programmable power supply voltage detector VPVD 2.56 2.59 V PLS[2:0]=101 (falling edge) 39
Programmable power supply voltage detector VPVD 2.76 2.8 V PLS[2:0]=110 (rising edge) 39
Programmable power supply voltage detector VPVD 2.65 2.69 V PLS[2:0]=110 (falling edge) 39
Programmable power supply voltage detector VPVD 2.87 2.91 V PLS[2:0]=111 (rising edge) 39
Programmable power supply voltage detector VPVD 2.75 2.79 V PLS[2:0]=111 (falling edge) 39

CAD (KiCad official)

  • Symbol: APM32E103RCT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: apm32e103rct6-etched.step / apm32e103rct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); apm32e103rct6.step / apm32e103rct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Geehy datasheet (72 pp, sha256 20b426b4f815178d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF