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APL5934KAI-TRG
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Anpec Elec Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAPL5934KAI-TRG
Anpec Elec · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP
APL5934KAI-TRG from Anpec Elec, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin of the circuitry; all voltage levels are measured with respect to this pin. |
| 2 | FB | input | Voltage feedback pin connected to an external resistor divider to set the output voltage against the 0.8V reference. |
| 3 | VOUT | power_out | Regulator output pin that requires at least 10μF of output capacitance for stability and can provide 3A (max.) load current. |
| 4 | VOUT | power_out | Regulator output pin that requires at least 10μF of output capacitance for stability and can provide 3A (max.) load current. |
| 5 | VIN | power_in | Main supply input for voltage conversion, with at least 10μF decoupling recommended and monitored for Power-On-Reset; VIN supply range is 1.2 to 5.5V. |
| 6 | VCNTL | power_in | Bias voltage input for internal control circuitry, recommended at +5V with 0.1μF decoupling; VCNTL supply range is 3.0 to 5.5V and it is monitored for Power-On-Reset. |
| 7 | POK | output | Open-drain power-OK output that is pulled low when the output voltage is not within the Power-OK voltage window. |
| 8 | EN | input | Active-high enable control pin; applying and holding a voltage below the enable threshold shuts down the output, and an internal 3μA current defines the level when left open. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Anpec Elec |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Supply Voltage (VIN to GND) | VIN | -0.3 | 6 | V | 4 | ||
| VCNTL Supply Voltage (VCNTL to GND) | VCNTL | -0.3 | 6 | V | 4 | ||
| VOUT to GND Voltage | VOUT | -0.3 | V | max VIN +0.3 V | 4 | ||
| POK to GND Voltage | POK | -0.3 | 6 | V | 4 | ||
| EN, FB to GND Voltage | EN, FB | -0.3 | V | max VCNTL +0.3 V | 4 | ||
| Power Dissipation | PD | 1.8 | W | TA=25°C | 4 | ||
| VOUT Peak Current | IOUT(PK) | 9 | A | <30μs | 4 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 4 | ||
| Maximum Lead Soldering Temperature, 10 Seconds | TSDR | 260 | °C | 10 seconds | 4 | ||
| VCNTL Supply Voltage | VCNTL | 3 | 5.5 | V | 4 | ||
| VIN Supply Voltage | VIN | 1.2 | 5.5 | V | 4 | ||
| VOUT Output Voltage | VOUT | 0.8 | V | when VCNTL-VOUT>1.9V; max VIN-VDROP | 4 | ||
| VOUT Output Current, Continuous Current | IOUT | 0 | 3 | A | Continuous Current | 4 | |
| VOUT Output Current, Peak Current | IOUT | 0 | 4 | A | Peak Current | 4 | |
| VOUT Output Capacitance | COUT | 8 | 1100 | μF | IOUT = 3A at 25% nominal VOUT | 4 | |
| VOUT Output Capacitance | COUT | 8 | 1700 | μF | IOUT = 2A at 25% nominal VOUT | 4 | |
| VOUT Output Capacitance | COUT | 8 | 2400 | μF | IOUT = 1A at 25% nominal VOUT | 4 | |
| ESR of VOUT Output Capacitor | ESRCOUT | 0 | 200 | mΩ | 4 | ||
| Ambient Temperature | TA | -40 | 85 | °C | 4 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 4 | ||
| VCNTL Supply Current | IVCNTL | 100 | 120 | μA | EN = High or ENB = Low, IOUT=0A | 5 | |
| VCNTL Supply Current at Shutdown | ISD | 3 | μA | EN = Low, or ENB = High | 5 | ||
| VIN Supply Current at Shutdown | 1 | μA | EN = Low, or ENB = High | 5 | |||
| Rising VCNTL POR Threshold | 2.5 | 2.7 | 2.9 | V | 5 | ||
| Rising VIN POR Threshold | 0.8 | 0.9 | 1 | V | 5 | ||
| Output Voltage Accuracy | -1.5 | 1.5 | % | VCNTL=3.0 ~ 5.5V, IOUT= 0 |
5 | ||
| Load Regulation | 0.06 | 0.25 | % | IOUT=0A ~3A | 5 | ||
| Line Regulation | 0.15 | 0.15 | %/V | IOUT=10mA, VCNTL= 3.0 ~ 5.5V | 5 | ||
| FB Input Current | VFB | -100 | 100 | nA | VFB=0.8V | 5 | |
| VIN-to-VOUT Dropout Voltage | VDROP | 0.26 | 0.31 | V | VCNTL=5.0V, IOUT=3A, VOUT=2.5V, TJ=25°C | 5 | |
| VIN-to-VOUT Dropout Voltage | VDROP | 0.42 | V | VCNTL=5.0V, IOUT=3A, VOUT=2.5V, TJ=-40~125°C | 5 | ||
| VIN-to-VOUT Dropout Voltage | VDROP | 0.24 | 0.29 | V | VCNTL=5.0V, IOUT=3A, VOUT=1.8V, TJ=25°C | 5 | |
| VIN-to-VOUT Dropout Voltage | VDROP | 0.4 | V | VCNTL=5.0V, IOUT=3A, VOUT=1.8V, TJ=-40~125°C | 5 | ||
| VIN-to-VOUT Dropout Voltage | VDROP | 0.23 | 0.28 | V | VCNTL=5.0V, IOUT=3A, VOUT=1.2V, TJ=25°C | 5 | |
| VIN-to-VOUT Dropout Voltage | VDROP | 0.38 | V | VCNTL=5.0V, IOUT=3A, VOUT=1.2V, TJ=-40~125°C | 5 | ||
| Current-Limit Level | ILIM | 4.7 | 5.7 | 6.7 | A | TJ=25°C | 5 |
| Current-Limit Level | ILIM | 4.2 | A | TJ= -40 ~ 125°C | 5 | ||
| Short Current-Limit Blanking Time | 0.6 | 1.5 | ms | From beginning of soft-start | 5 | ||
| Thermal Shutdown Temperature | TSD | 145 | 150 | °C | TJ rising | 5 | |
| EN Logic High Threshold Voltage / ENB Logic Low Threshold Voltage | VEN/VENB | 0.5 | 0.8 | 1.1 | V | VEN rising or VENB rising | 6 |
| Soft-Start Interval | tSS | 0.3 | 0.6 | 1.2 | ms | VOUT=10% to 90% (APL5934/B/C) | 6 |
| Turn On Delay | tON | 60 | 120 | 230 | μs | From being enabled to VOUT rising 10% (APL5934/C) | 6 |
| Rising POK Threshold Voltage | VTHPOK | 90 | 92 | 94 | % | VFB rising | 6 |
| POK Pull-low Voltage | 0.25 | 0.4 | V | POK sinks 5mA | 6 | ||
| POK Delay Time | 1 | 2 | 4 | ms | From VFB =VTHPOK to rising edge of the VPOK | 6 | |
| VCNTL POR Hysteresis | 0.4 | V | 5 | ||||
| VIN POR Hysteresis | 0.5 | V | 5 | ||||
| Reference Voltage | VREF | 0.8 | V | FB=VOUT | 5 | ||
| VOUT Pull-low Resistance | 85 | Ω | VCNTL=5V, VEN=0V, VOUT<0.8V | 5 | |||
| Short Current-Limit Level | ISHORT | 1.1 | A | VFB<0.2V | 5 | ||
| EN/ENB Hysteresis | 0.1 | V | 6 | ||||
| EN/ENB Pull-High / Pull-Low Current | 3 | μA | EN=GND or ENB = GND (pull-high); EN=VCNTL or ENB = VCNTL (pull-low) | 6 | |||
| POK Threshold Hysteresis | 8 | % | 6 | ||||
| POK Debounce Interval | 10 | μs | VFB<falling POK voltage threshold | 6 | |||
| Thermal Shutdown Hysteresis | 50 | °C | 5 | ||||
| Junction-to-Ambient Resistance in Free Air, SOP-8P | θJA | 50 | °C/W | Note 2: measured on high effective thermal conductivity test board in free air | 4 | ||
| Junction-to-Case Resistance in Free Air, SOP-8P | θJC | 18 | °C/W | Note 2: measured on high effective thermal conductivity test board in free air | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 3 | |
| contacts | tin | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 3 |
CAD (KiCad official)
- Symbol:
APL5934KAI-TRG - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
apl5934kai-trg-etched.step/apl5934kai-trg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apl5934kai-trg.step/apl5934kai-trg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Anpec Elec datasheet (24 pp, sha256
629fcaf4c28f7105, retrieved 2026-11-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).