component
APL5912KAC-TRG
Public Made by Adomby adom
Anpec Elec Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "Anpec Elec Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"power management (pmic)",
"apl5912kac-trg",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"apl5912kac-trg.kicad_sym",
"apl5912kac-trg.kicad_mod",
"apl5912kac-trg.glb",
"apl5912kac-trg.step",
"apl5912kac-trg.lbr",
"docs/hero.png",
"docs/apl5912kac-trg-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"apl5912kac-trg-hero.glb",
"apl5912kac-trg-hero.overlay.json",
"apl5912kac-trg-etched.glb"
],
"component": {
"mpn": "APL5912KAC-TRG",
"manufacturer": "Anpec Elec",
"package": "SOP-8-EP",
"pin_count": 9,
"category": "Power Management (PMIC)",
"subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911716851986432",
"parts": {
"symbol": "apl5912kac-trg.kicad_sym",
"footprint": "apl5912kac-trg.kicad_mod",
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"model_3d_step": "apl5912kac-trg-etched.step",
"model_3d_step_plain": "apl5912kac-trg.step",
"lbr": "apl5912kac-trg.lbr"
},
"distributor_links": {
"lcsc": "C347521"
},
"distributor_check": {
"checked_at": "2026-10-18T11:26:41Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "quota"
},
"mouser": {
"pn": null,
"status": "quota"
}
},
"pins": [
{
"number": "1",
"name": "GND",
"type": "power_in",
"description": "Ground pin of the circuitry; all voltage levels are measured with respect to this pin."
},
{
"number": "2",
"name": "FB",
"type": "input",
"description": "Feedback input from an external resistor divider, with VOUT = 0.8 V × (1 + R2/R1), where R1 runs from VOUT to FB (Kelvin sensed) and R2 from FB to GND."
},
{
"number": "3",
"name": "VOUT",
"type": "power_out",
"description": "Regulator output; pins 3 and 4 must be tied together with wide tracks and an output capacitor connected to this pin for closed-loop compensation and transient response."
},
{
"number": "4",
"name": "VOUT",
"type": "power_out",
"description": "Regulator output; connect together with pin 3 using wide tracks and place the output capacitor on this pin for compensation and transient response."
},
{
"number": "5",
"name": "VIN",
"type": "power_in",
"description": "Main supply input for power conversion (1.0 to 3.4 V recommended), also monitored for power-on-reset with a rising threshold of 0.8 to 0.99 V."
},
{
"number": "6",
"name": "VCNTL",
"type": "power_in",
"description": "Power input for the control circuitry, with +5 V recommended and a 3.1 to 6 V recommended operating range, also monitored for power-on-reset with a rising threshold of 2.7 to 3.1 V."
},
{
"number": "7",
"name": "POK",
"type": "output",
"description": "Open-drain power-OK output that is pulled low when the FB voltage is outside the POK thresholds, indicating the output is not OK."
},
{
"number": "8",
"name": "EN",
"type": "input",
"description": "Enable input; pulling and holding it below 0.3 V shuts down the output, and when left open an internal 10 µA source pulls it up to VCNTL to enable the regulator."
},
{
"number": "9",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The exposed thermal pad on the SOP-8P is not given a pin number in the datasheet pin table or the pi; The datasheet's exposed-pad description says to tie the exposed pad and 'VIN Pin (Pin 8)' together, ; Pin 1 is GND, and the pin-configuration drawing on page 1 lists labels in a sequence that does not m",
"exposed pad 9 added from the footprint"
],
"pages_sent": 20,
"cost_usd": 0.0928,
"at": "2026-10-18T11:25:38"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911716851986432",
"pages": 20,
"sha256": "3f404942a5d32f7b",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 9,
"described": 9,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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"role": "plain",
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"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
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"footprint_binding": "identity",
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"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "apl5912kac-trg-etched.step",
"role": "eda",
"up": "Z",
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"seat": "z = 0",
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"sha256": "71ce2250c55aed804498efa7556422c5bef9bcb4e507bd6962a596be0be12916",
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}