component
APL5912KAC-TRG
Public Made by Adomby adom
Anpec Elec Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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APL5912KAC-TRG
Anpec Elec · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP
APL5912KAC-TRG from Anpec Elec, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin of the circuitry; all voltage levels are measured with respect to this pin. |
| 2 | FB | input | Feedback input from an external resistor divider, with VOUT = 0.8 V × (1 + R2/R1), where R1 runs from VOUT to FB (Kelvin sensed) and R2 from FB to GND. |
| 3 | VOUT | power_out | Regulator output; pins 3 and 4 must be tied together with wide tracks and an output capacitor connected to this pin for closed-loop compensation and transient response. |
| 4 | VOUT | power_out | Regulator output; connect together with pin 3 using wide tracks and place the output capacitor on this pin for compensation and transient response. |
| 5 | VIN | power_in | Main supply input for power conversion (1.0 to 3.4 V recommended), also monitored for power-on-reset with a rising threshold of 0.8 to 0.99 V. |
| 6 | VCNTL | power_in | Power input for the control circuitry, with +5 V recommended and a 3.1 to 6 V recommended operating range, also monitored for power-on-reset with a rising threshold of 2.7 to 3.1 V. |
| 7 | POK | output | Open-drain power-OK output that is pulled low when the FB voltage is outside the POK thresholds, indicating the output is not OK. |
| 8 | EN | input | Enable input; pulling and holding it below 0.3 V shuts down the output, and when left open an internal 10 µA source pulls it up to VCNTL to enable the regulator. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Anpec Elec |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCNTL Supply Voltage | VCNTL | 3.1 | 6 | V | 3 | ||
| VIN Supply Voltage | VIN | 1 | 3.4 | V | 3 | ||
| Output Voltage | VOUT | 0.8 | 1.2 | V | VCNTL=3.3±5% | 3 | |
| Output Voltage | VOUT | 0.8 | V | VCNTL=5.0±5%; printed max is VIN-0.2 V | 3 | ||
| VOUT Output Current | IOUT | 0 | 6 | A | 3 | ||
| Junction Temperature (recommended) | TJ | -25 | 125 | oC | 3 | ||
| VCNTL Supply Voltage (VCNTL to GND) | VCNTL | -0.3 | 7 | V | 2 | ||
| VIN Supply Voltage (VIN to GND) | VIN | -0.3 | 3.5 | V | 2 | ||
| EN and FB to GND | VI/O | -0.3 | V | printed max is VCNTL+0.3 V | 2 | ||
| POK to GND | VPOK | -0.3 | 7 | V | 2 | ||
| Power Dissipation | PD | 3 | W | 2 | |||
| Junction Temperature | TJ | 150 | oC | 2 | |||
| Storage Temperature | TSTG | -65 | 150 | oC | 2 | ||
| Maximum Lead Soldering Temperature | TSDR | 260 | oC | 10 seconds | 2 | ||
| VCNTL Supply Current | ICNTL | 0.4 | 1 | 2 | mA | EN = VCNTL, VFB is well regulated | 3 |
| VCNTL Shutdown Current | ISD | 180 | 380 | μA | EN = GND | 3 | |
| VCNTL POR Threshold | 2.7 | 2.9 | 3.1 | V | VCNTL Rising | 3 | |
| VIN POR Threshold | 0.8 | 0.9 | 0.99 | V | VIN Rising | 3 | |
| Output Voltage Accuracy | -1.5 | 1.5 | % | IOUT=0A ~ 5A, TJ= -25 ~125oC | 3 | ||
| Line Regulation | -0.13 | 0.13 | %/V | VCNTL=3.3 ~ 5.5V | 3 | ||
| Load Regulation | 0.06 | 0.15 | % | IOUT=0A ~ 5A | 3 | ||
| Dropout Voltage | 0.15 | 0.2 | V | IOUT = 5A, VCNTL=5V, TJ= 25oC | 3 | ||
| Dropout Voltage | 0.25 | V | IOUT = 5A, VCNTL=5V, TJ= -25~125oC | 3 | |||
| Current Limit | ILIM | 7 | 8 | 9 | A | VCNTL=5V, TJ= 25oC | 3 |
| Current Limit | ILIM | 6 | A | VCNTL=5V, TJ= -25 ~ 125oC | 3 | ||
| Current Limit | ILIM | 6.8 | 7.8 | 8.8 | A | VCNTL=3.3V, TJ= 25oC | 3 |
| EN Logic High Threshold Voltage | 0.3 | 0.4 | 0.5 | V | VEN Rising | 4 | |
| POK Threshold Voltage for Power OK | VPOK | 90 | 92 | 94 | %VREF | VFB Rising | 4 |
| POK Threshold Voltage for Power Not OK | VPNOK | 79 | 81 | 83 | %VREF | VFB Falling | 4 |
| POK Low Voltage | 0.25 | 0.4 | V | POK sinks 5mA | 4 | ||
| POK Delay Time | TDELAY | 1 | 3 | 10 | ms | 4 | |
| Junction-to-Ambient Thermal Resistance in Free Air (SOP-8P) | θJA | 40 | oC/W | Mounted on high effective thermal conductivity test board in free air; exposed pad soldered to PCB (Note 2) | 2 | ||
| Junction-to-Case Thermal Resistance (SOP-8P) | θJC | 17 | oC/W | Thermal pad temperature measured on PCB copper (Note 3) | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 | |
| contacts | tin | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 |
CAD (KiCad official)
- Symbol:
APL5912KAC-TRG - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
apl5912kac-trg-etched.step/apl5912kac-trg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apl5912kac-trg.step/apl5912kac-trg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Anpec Elec datasheet (20 pp, sha256
3f404942a5d32f7b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# APL5912KAC-TRG
**Anpec Elec** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP
APL5912KAC-TRG from Anpec Elec, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin of the circuitry; all voltage levels are measured with respect to this pin. |
| 2 | FB | input | Feedback input from an external resistor divider, with VOUT = 0.8 V × (1 + R2/R1), where R1 runs from VOUT to FB (Kelvin sensed) and R2 from FB to GND. |
| 3 | VOUT | power_out | Regulator output; pins 3 and 4 must be tied together with wide tracks and an output capacitor connected to this pin for closed-loop compensation and transient response. |
| 4 | VOUT | power_out | Regulator output; connect together with pin 3 using wide tracks and place the output capacitor on this pin for compensation and transient response. |
| 5 | VIN | power_in | Main supply input for power conversion (1.0 to 3.4 V recommended), also monitored for power-on-reset with a rising threshold of 0.8 to 0.99 V. |
| 6 | VCNTL | power_in | Power input for the control circuitry, with +5 V recommended and a 3.1 to 6 V recommended operating range, also monitored for power-on-reset with a rising threshold of 2.7 to 3.1 V. |
| 7 | POK | output | Open-drain power-OK output that is pulled low when the FB voltage is outside the POK thresholds, indicating the output is not OK. |
| 8 | EN | input | Enable input; pulling and holding it below 0.3 V shuts down the output, and when left open an internal 10 µA source pulls it up to VCNTL to enable the regulator. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Anpec Elec |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCNTL Supply Voltage | VCNTL | 3.1 | | 6 | V | | 3 |
| VIN Supply Voltage | VIN | 1 | | 3.4 | V | | 3 |
| Output Voltage | VOUT | 0.8 | | 1.2 | V | VCNTL=3.3±5% | 3 |
| Output Voltage | VOUT | 0.8 | | | V | VCNTL=5.0±5%; printed max is VIN-0.2 V | 3 |
| VOUT Output Current | IOUT | 0 | | 6 | A | | 3 |
| Junction Temperature (recommended) | TJ | -25 | | 125 | oC | | 3 |
| VCNTL Supply Voltage (VCNTL to GND) | VCNTL | -0.3 | | 7 | V | | 2 |
| VIN Supply Voltage (VIN to GND) | VIN | -0.3 | | 3.5 | V | | 2 |
| EN and FB to GND | VI/O | -0.3 | | | V | printed max is VCNTL+0.3 V | 2 |
| POK to GND | VPOK | -0.3 | | 7 | V | | 2 |
| Power Dissipation | PD | | | 3 | W | | 2 |
| Junction Temperature | TJ | | | 150 | oC | | 2 |
| Storage Temperature | TSTG | -65 | | 150 | oC | | 2 |
| Maximum Lead Soldering Temperature | TSDR | | | 260 | oC | 10 seconds | 2 |
| VCNTL Supply Current | ICNTL | 0.4 | 1 | 2 | mA | EN = VCNTL, VFB is well regulated | 3 |
| VCNTL Shutdown Current | ISD | | 180 | 380 | μA | EN = GND | 3 |
| VCNTL POR Threshold | | 2.7 | 2.9 | 3.1 | V | VCNTL Rising | 3 |
| VIN POR Threshold | | 0.8 | 0.9 | 0.99 | V | VIN Rising | 3 |
| Output Voltage Accuracy | | -1.5 | | 1.5 | % | IOUT=0A ~ 5A, TJ= -25 ~125oC | 3 |
| Line Regulation | | -0.13 | | 0.13 | %/V | VCNTL=3.3 ~ 5.5V | 3 |
| Load Regulation | | | 0.06 | 0.15 | % | IOUT=0A ~ 5A | 3 |
| Dropout Voltage | | | 0.15 | 0.2 | V | IOUT = 5A, VCNTL=5V, TJ= 25oC | 3 |
| Dropout Voltage | | | | 0.25 | V | IOUT = 5A, VCNTL=5V, TJ= -25~125oC | 3 |
| Current Limit | ILIM | 7 | 8 | 9 | A | VCNTL=5V, TJ= 25oC | 3 |
| Current Limit | ILIM | 6 | | | A | VCNTL=5V, TJ= -25 ~ 125oC | 3 |
| Current Limit | ILIM | 6.8 | 7.8 | 8.8 | A | VCNTL=3.3V, TJ= 25oC | 3 |
| EN Logic High Threshold Voltage | | 0.3 | 0.4 | 0.5 | V | VEN Rising | 4 |
| POK Threshold Voltage for Power OK | VPOK | 90 | 92 | 94 | %VREF | VFB Rising | 4 |
| POK Threshold Voltage for Power Not OK | VPNOK | 79 | 81 | 83 | %VREF | VFB Falling | 4 |
| POK Low Voltage | | | 0.25 | 0.4 | V | POK sinks 5mA | 4 |
| POK Delay Time | TDELAY | 1 | 3 | 10 | ms | | 4 |
| Junction-to-Ambient Thermal Resistance in Free Air (SOP-8P) | θJA | | 40 | | oC/W | Mounted on high effective thermal conductivity test board in free air; exposed pad soldered to PCB (Note 2) | 2 |
| Junction-to-Case Thermal Resistance (SOP-8P) | θJC | | 17 | | oC/W | Thermal pad temperature measured on PCB copper (Note 3) | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 |
| contacts | | tin | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 |
## CAD (KiCad official)
- Symbol: `APL5912KAC-TRG`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `apl5912kac-trg-etched.step` / `apl5912kac-trg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `apl5912kac-trg.step` / `apl5912kac-trg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Anpec Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911716851986432) (20 pp, sha256 `3f404942a5d32f7b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/apl5912kac-trg-datasheet.pdf)