component
APL5607AKI-TRG
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Anpec Elec Linear Voltage Regulators (LDO), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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APL5607AKI-TRG
Anpec Elec · Linear Voltage Regulators (LDO) · SOP-8
APL5607AKI-TRG from Anpec Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input: driving EN high turns on the regulator, pulling it low enters shutdown mode, and it is pulled low by an internal resistor (APL5607) or high (APL5607A). |
| 2 | VIN | power_in | Supply voltage input ranging from 4.5V to 6V, to be bypassed with a 2.2μF (typical) capacitor to GND. |
| 3 | VOUT | power_out | Regulator output sourcing up to 600mA, requiring a small capacitor to ground to assure stability. |
| 4 | VSET | input | Output voltage-set input; the output voltage follows 1.6 times the VSET voltage. |
| 5 | GND | power_in | Ground, internally connected to the leadframe; connect to a wide ground plane for good heat dissipation. |
| 6 | GND | power_in | Ground, internally connected to the leadframe; connect to a wide ground plane for good heat dissipation. |
| 7 | GND | power_in | Ground, internally connected to the leadframe; connect to a wide ground plane for good heat dissipation. |
| 8 | GND | power_in | Ground, internally connected to the leadframe; connect to a wide ground plane for good heat dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Anpec Elec |
| Package | SOP-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | VIN | -0.3 | 6.5 | V | 2 | ||
| EN to GND | VEN | -0.3 | V | max VIN+0.3 | 2 | ||
| VOUT to GND | VOUT | -0.3 | V | max VIN+0.3 | 2 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Maximum Lead Soldering Temperature | TSDR | 260 | °C | 10 Seconds | 2 | ||
| Input voltage | VIN | 4.5 | 6 | V | VIN to GND | 2 | |
| EN voltage | VEN | 0 | V | max VIN | 2 | ||
| VSET voltage | VSET | 0 | 3.3 | V | VSET to GND | 2 | |
| Output Current | IOUT | 0 | 0.6 | A | 3 | ||
| Input Capacitor | CIN | 2.2 | 470 | μF | 3 | ||
| Output Capacitor | COUT | 2.2 | 330 | μF | 3 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Shutdown Supply Current | IQ | 1 | μA | VEN = 0V | 3 | ||
| Quiescent Current | IQ | 140 | 200 | μA | VEN = 5V, IOUT = 0A | 3 | |
| VIN UVLO Threshold | 2.5 | 2.9 | 3.3 | V | VIN rising | 3 | |
| VOUT Voltage / VSET Voltage | 1.552 | 1.6 | 1.648 | V/V | TJ=25°C, VIN=5.5V, IOUT=1mA, VSET=3.3V | 3 | |
| VOUT Voltage / VSET Voltage | 1.504 | 1.6 | 1.696 | V/V | TJ=40 ~ 125°C, VIN=5.5V, IOUT=1mA, VSET=1 ~ 3.3V | 3 | |
| VSET Pin Current | 0.05 | 1 | μA | VSET=5V | 3 | ||
| Load Regulation | 60 | 100 | mV | IOUT=1mA to 600mA | 3 | ||
| Dropout Voltage | VDROP | 200 | 320 | mV | IOUT=600mA, VOUT=5V | 3 | |
| Output Current-Limit | 700 | mA | 3 | ||||
| Soft-Start Time | TSS | 130 | 300 | μs | VIN=0 to 5V, VEN=VIN | 3 | |
| EN Logic Input-High Level | 1.6 | V | 3 | ||||
| EN Logic Input-Low Level | 0.4 | V | 3 | ||||
| VIN UVLO Hysteresis | 0.15 | V | 3 | ||||
| Thermal Shutdown Temperature | 150 | °C | 3 | ||||
| Thermal Shutdown Hysteresis | 40 | °C | 3 | ||||
| Foldback Current-Limit | 250 | mA | VOUT < 0.6V | 3 | |||
| VOUT Pull Low Resistance | 60 | Ω | VEN=0V, VOUT=0.5V | 3 | |||
| EN Pull-High Resistance | 390 | kΩ | APL5607A | 3 | |||
| Junction to Ambient Thermal Resistance SOP-8 | θJA | 80 | °C/W | SOP-8, component mounted on high effective thermal conductivity test board in free air | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 | |
| contacts | tin | Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed | 2 |
CAD (KiCad official)
- Symbol:
APL5607AKI-TRG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
apl5607aki-trg-etched.step/apl5607aki-trg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apl5607aki-trg.step/apl5607aki-trg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Anpec Elec datasheet (16 pp, sha256
77c1794f27149e71, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).