component

AP7381-50SA-7

Public Made by Adom

by adom

Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
Name Last commit message Last updated
docs ap7381-50sa-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ap7381-50sa-7-etched.fit.json ap7381-50sa-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ap7381-50sa-7-etched.glb ap7381-50sa-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ap7381-50sa-7-etched.step ap7381-50sa-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ap7381-50sa-7.glb Publish 0.1.0 · Ray
ap7381-50sa-7.kicad_mod Publish 0.1.0 · Ray
ap7381-50sa-7.kicad_sym Publish 0.1.0 · Ray
ap7381-50sa-7.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ap7381-50sa-7.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json ap7381-50sa-7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md ap7381-50sa-7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

AP7381-50SA-7

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23

AP7381-50SA-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Unregulated supply input voltage. Recommended operating range 3.3V to 40V (absolute maximum -0.3V to 45V). A 1µF ceramic bypass capacitor to GND is recommended near the pin.
2 VOUT power_out Regulated 5.0V output (fixed, -50 variant). Delivers up to 150mA with typical dropout of 1000mV @ 100mA. Requires a 2.2µF low-ESR ceramic output capacitor to GND for stability.
3 GND power_in Device ground reference. Typical quiescent ground current is 2.5µA at no load and ~25µA at 100mA load.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category PMIC
Pins 3

Ordering variants

  • AP7381-50SA-7
  • AP7381-50SA-728Y-13
  • AP7381-50SA-733Y-13
  • AP7381-50SA-750Y-13
  • AP7381-50SA-770Y-13
  • AP7381-50SA-733Y-TC
  • AP7381-50SA-728V-A
  • AP7381-50SA-733V-A
  • AP7381-50SA-750V-A
  • AP7381-50SA-770V-A

CAD (KiCad official)

  • Symbol: AP7381-50SA-7
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ap7381-50sa-7-etched.step / ap7381-50sa-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap7381-50sa-7.step / ap7381-50sa-7.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ap7381-50sa-7.step 59 KB You want the bare part, or you mark your own boards.
ap7381-50sa-7-etched.step 2.1 MB You want the part with AP7381-50SA-7 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 514 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (13 pp, sha256 657d25b1f48ab5dc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF