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docs ap7365-18wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
ap7365-18wg-7-etched.fit.json ap7365-18wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7365-18wg-7-etched.glb ap7365-18wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7365-18wg-7-etched.step ap7365-18wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7365-18wg-7.glb Publish 0.1.0 · Ray 2mo ago
ap7365-18wg-7.kicad_mod Publish 0.1.0 · Ray 2mo ago
ap7365-18wg-7.kicad_sym Publish 0.1.0 · Ray 2mo ago
ap7365-18wg-7.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray 2mo ago
ap7365-18wg-7.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
page.json ap7365-18wg-7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 27d ago
README.md ap7365-18wg-7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

AP7365-18WG-7

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25

AP7365-18WG-7 from Diodes Incorporated, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Voltage input pin, 2V to 6V. Bypass to ground with at least a 1µF MLCC capacitor close to the pin. Absolute-maximum input voltage is 6.5V.
2 GND power_in Device ground reference and return for the pass element and internal reference. Connect to the system ground plane.
3 EN input Enable input, active high. VIH ≥ 1.4V turns the regulator on; VIL ≤ 0.4V shuts it down (IQ drops to ~0.1µA typical shutdown current). Do not leave floating; can be tied to IN for always-on operation. Absolute max VEN = VIN + 0.3V.
4 NC unconnected No internal connection. May be left floating or tied to GND for mechanical/PCB robustness.
5 OUT power_out Regulated voltage output pin, fixed 1.8V for the -18 option. Sources up to 600mA. Bypass to ground with a 1µF (or greater) low-ESR MLCC capacitor for stability and load-transient response.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-25
Category PMIC
Pins 5

Ordering variants

  • AP7365-18WG-7W
  • AP7365-18WG-7SN
  • AP7365-18WG-7Y
  • AP7365-18WG-7YR
  • AP7365-18WG-7E
  • AP7365-18WG-7ER
  • AP7365-18WG-7EV

CAD (KiCad official)

  • Symbol: AP7365-18WG-7
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-25 (KiCad packages3D, STEP)
  • 3D model files: ap7365-18wg-7-etched.step / ap7365-18wg-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap7365-18wg-7.step / ap7365-18wg-7.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ap7365-18wg-7.step 85 KB You want the bare part, or you mark your own boards.
ap7365-18wg-7-etched.step 2.2 MB You want the part with AP7365-18WG-7 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 533 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (18 pp, sha256 7ec2b65a0dbeaec0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF